26.7.4 Synchronization Busy
| Name: | SYNCBUSY |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ENABLE | SWRST | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 1 – ENABLE Enable Synchronization Busy Status
Important: SYNCBUSY.ENABLE
bit is functional for level detection and asynchronous edge detection modes. For
synchronous edge detection mode, it is required to wait for three cycles of the
selected clock (GCLK_EIC or CLK_ULP32K) once SYNCBUSY.ENABLE bit is cleared; then
clear INTFLAG register and configure INTENSET if required.
| Value | Description |
|---|---|
| 0 | Write synchronization for CTRLA.ENABLE bit is complete. |
| 1 | Write synchronization for CTRLA.ENABLE bit is ongoing. |