7.3 SRAM Map

The variables located in the SRAM contain all necessary information to control the receiver in IDLEMode, RXMode and PollingMode. During start-up, the variables will be loaded with the configuration stored in the EEPROM automatically.

Table 7-2. SRAM Map
Object Name {Type}AddressSizeDescription
SubObjects {Type}StartEnd[Bytes]Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
extIf {sIFData}15————————
—tmp[2]{volatile uint8_t}0x02000x02012Used as temporary variable for address storing (low byte and high byte)
—pcInt0[2]{pcIntHandler}0x02020x02032Function pointer used for PinChangeINT0 interrupt (low byte and high byte)
—pcInt1[2]{pcIntHandler}0x02040x02052Function pointer used for PinChangeINT1 interrupt (low byte and high byte)
—pcInt0old{uint8_t}0x0206—1Old value of pcint0, to detect which pin caused the event
—pcInt1old{uint8_t}0x0207—1Old value of pcint1, to detect which pin caused the event
—irqInt0[2]{irqIntHandler}0x02080x02092Function pointer used for INT0 interrupt (low byte and high byte)
—flashPtr[2]{flashFunc}0x020A0x020B2Function pointer used for “Patch SPI” command (low byte and high byte)
— addressPtr[2] {volatile uint8_t} 0x020C0x020D2Used as address pointer for storing addresses of a SPI block read/write command (low byte and high byte)
—length{volatile uint8_t}0x020E—1Used as length indicator in SPI block read/write commands
events {sEventData}8——————
— pinEventMask {pinEventConfig_t} 0x020F—1PWRON—NPWRON6NPWRON5NPWRON4NPWRON3NPWRON2NPWRON1
— sysEventMask {sysEventConfig_t} 0x0210—1SYS_ERR—SYS_RDYAVCCLOWLOWBATT RX_ACTIVE_EN RX_ACTIVE_POL IRQ_POL
—cmdRdyConf{uint8_t}0x0211—1ANT_TUNETEMP_MEASSRC_CALFRC_CALVCO_CALRF_CALSELFCHECKTX
—eventCopy[0] {uint8_t}0x0212—1SYS_ERRCMD_RDYSYS_RDYAVCCLOWLOWBATTSFIFODFIFO_RXDFIFO_TX
—eventCopy[1] {uint8_t}0x0213—1ID_CHECKAWCOKASOTAEOTAID_CHECKBWCOKBSOTBEOTB
—eventCopy[2] {uint8_t}0x0214—1PWRON—NPWRON6NPWRON5NPWRON4NPWRON3NPWRON2NPWRON1
—eventCopy[3] {uint8_t}0x0215—1enaPathBenaPathACh[1:0]—Ser[2:0]
—eventCtrl{uint8_t}0x0216—1———————EVENT_PENDING
currentService {sCurrentServiceConfiguration}126————————
—CHCR{uint8_t}0x0217—1————BWM[3:0]
—CHDN{uint8_t}0x0218—1——ADCDNBBDN[4:0]
— CHSTARTFILTER {uint8_t} 0x0219—1——PLDTHADTDFDTFID[2:0]
—DMCDA{uint8_t}0x021A—1DMCTA[2:0]DMCLA[4:0]
—DMCDB{uint8_t}0x021B—1DMCTB[2:0]DMCLB[4:0]
—DMCRA{uint8_t}0x021C—1DMARASY1TASASKADMPGA[4:0]
—DMCRB{uint8_t}0x021D—1DMARBSY1TBSASKBDMPGB[4:0]
—DMDRA{uint8_t}0x021E—1DMDNA[3:0]DMAA[3:0]
—DMDRB{uint8_t}0x021F—1DMDNB[3:0]DMAB[3:0]
—DMMA{uint8_t}0x0220—1DMNEADMHADMPADMATA[4:0]
—DMMB{uint8_t}0x0221—1DMNEBDMHBDMPBDMATB[4:0]
—EOT1A{uint8_t}0x0222—1EOTBFERRFEATELREATMOFEAMANFEASYTFEAAMPFEACARFEA
—EOT1B{uint8_t}0x0223—1EOTAFERRFEBTELREBTMOFEBMANFEBSYTFEBAMPFEBCARFEB
—EOT2A{uint8_t}0x0224—1EOTBFERRFEATELREATMOFEAMANFEASYTFEAAMPFEACARFEA
—EOT2B{uint8_t}0x0225—1EOTAFERRFEBTELREBTMOFEBMANFEBSYTFEBAMPFEBCARFEB
—EOT3A{uint8_t}0x0226—1EOTBFERRFEATELREATMOFEAMANFEASYTFEAAMPFEACARFEA
—EOT3B{uint8_t}0x0227—1EOTAFERRFEBTELREBTMOFEBMANFEBSYTFEBAMPFEBCARFEB
—FEALR_FEANT{uint8_t}0x0228—1——FEALR.RNGE[1:0]FEANT.LVLC[3:0]
—FEAT{uint8_t}0x0229—1————ANTN[3:0]
—FEPAC{uint8_t}0x022A—1PACR[7:0]
—FEVCO{uint8_t}0x022B—1VCOB[3:0]CPCC[3:0]
—FEVCT{uint8_t}0x022C—1————FEVCT[3:0]
—FREQoffset[0] {uint8_t}0x022D—1FREQoffset[7:0]
—FREQoffset[1] {uint8_t}0x022E—1FREQoffset[15:8]
—txDevA[0] {uint8_t}0x022F—1txDevA[7:0]
—txDevA[1] {uint8_t}0x0230—1txDevA[15:8]
—txDevB[0] {uint8_t}0x0231—1txDevB[7:0]
—txDevB[1] {uint8_t}0x0232—1txDevB[15:8]
—GACDIVA[0] {uint8_t}0x0233—1GACDIVL[7:0]
—GACDIVA[1] {uint8_t}0x0234—1———GACDIVH[4:0]
—GACDIVB[0] {uint8_t}0x0235—1GACDIVL[7:0]
—GACDIVB[1] {uint8_t}0x0236—1———GACDIVH[4:0]
—IF[0] {uint8_t}0x0237—1IF[7:0]
—IF[1] {uint8_t}0x0238—1IF[15:8]
—RDOCR{uint8_t}0x0239—1—00ETRPBETRPATMDS[1:0]—
—rssiSysConf{uint8_t}0x023A—1RssiEnable—rssiBufEvMaskRSSIbuf[4:0]
—rxSetPathA[0] {uint8_t}0x023B—1—rxBufEvMaskARXbufA[5:0]
—rxSetPathA[1] {uint8_t}0x023C—1IWUPADARAGAPMARXTEHA———RXMODA
—rxSetPathB[0] {uint8_t}0x023D—1—rxBufEvMaskBRXbufB[5:0]
—rxSetPathB[1] {uint8_t}0x023E—1IWUPBDARBGAPMBRXTEHB———RXMODB
—rxSysEvent{uint8_t}0x023F—1 IDCHKA_Mask WCOKA_Mask SOTA_Mask EOTA_Mask IDCHKB_Mask WCOKB_Mask SOTB_Mask EOTB_Mask
—rxSysSet{uint8_t}0x0240—1subChanneling_ENAIdScan_ENAIFAmplifier_ENA PathValidAfterSOT_ENAAntDampPathB_disableAntDampPathA_disable Switching_SDTX Switching_SDRX
—SFIDA[0] {uint8_t}0x0241—1SFID1A[7:0]
—SFIDA[1] {uint8_t}0x0242—1SFID2A[7:0]
—SFIDA[2] {uint8_t}0x0243—1SFID3A[7:0]
—SFIDA[3] {uint8_t}0x0244—1SFID4A[7:0]
—SFIDB[0] {uint8_t}0x0245—1SFID1B[7:0]
—SFIDB[1] {uint8_t}0x0246—1SFID2B[7:0]
—SFIDB[2] {uint8_t}0x0247—1SFID3B[7:0]
—SFIDB[3] {uint8_t}0x0248—1SFID4B[7:0]
—SFIDCA{uint8_t}0x0249—1SEMEA——SFIDTA[4:0]
—SFIDCB{uint8_t}0x024A—1SEMEB——SFIDTB[4:0]
—SFIDLA{uint8_t}0x024B—1——SFIDLA[5:0]
—SFIDLB{uint8_t}0x024C—1——SFIDLB[5:0]
—SOT1A{uint8_t}0x024D—1WCOBOERROEASFIDEAWUPEAMANOEASYTOEAAMPOEACAROEA
—SOT1B{uint8_t}0x024E—1WCOAOERROEBSFIDEBWUPEBMANOEBSYTOEBAMPOEBCAROEB
—SOT2A{uint8_t}0x024F—1WCOBOERROEASFIDEAWUPEAMANOEASYTOEAAMPOEACAROEA
—SOT2B{uint8_t}0x0250—1WCOAOERROEBSFIDEBWUPEBMANOEBSYTOEBAMPOEBCAROEB
—SOTtimeOutA{uint8_t}0x0251—1SOTTOA[7:0]
—SOTtimeOutB{uint8_t}0x0252—1SOTTOB[7:0]
—SYCA{uint8_t}0x0253—1SYTLA[3:0]SYCSA[3:0]
—SYCB{uint8_t}0x0254—1SYTLB[3:0]SYCSB[3:0]
—FSFCRA{uint8_t}0x0255—1ASDIV[3:0]——BTSEL[1:0]
—FSFCRB{uint8_t}0x0256—1ASDIV[3:0]——BTSEL[1:0]
—TMUL{uint8_t}0x0257—1TMUL[7:0]
—trxSysConf{uint8_t}0x0258—1————TRPB_ENATRPA_ENAAntennaSwitching_ENAChannelSwitch_ENA
—TXDRA[0] {uint8_t}0x0259—1TXDRA[7:0]
—TXDRA[1] {uint8_t}0x025A—1TXDRA[15:8]
—TXDRB[0] {uint8_t}0x025B—1TXDRB[7:0]
—TXDRB[1] {uint8_t}0x025C—1TXDRB[15:8]
—txSetPathA[0] {uint8_t}0x025D—1GAUSPREEStartTxFillLevelA[5:0]
—txSetPathA[1] {uint8_t}0x025E—1TXMODAASKshapingenable—StartPreambleFillLevelA[4:0]
—txSetPathB[0] {uint8_t}0x025F—1GAUSPREEStartTxFillLevelB[5:0]
—txSetPathB[1] {uint8_t}0x0260—1TXMODBASKshapingenable—StartPreambleFillLevelB[4:0]
—txSysEventA{uint8_t}0x0261—1TX_EndingtxBufEvMaskATxBufFillLevelA[5:0]
—txSysEventB{uint8_t}0x0262—1TX_EndingtxBufEvMaskBTxBufFillLevelB[5:0]
— txPreambleSysEventA {uint8_t} 0x0263—1——txPreambleBufEv MaskAPreambleBufFillLevelA[4:0]
— txPreambleSysEventB {uint8_t} 0x0264—1——txPreambleBufEv MaskBPreambleBufFillLevelB[4:0]
—WCOtimeOutA{uint8_t}0x0265—1WCOTOA[7:0]
—WCOtimeOutB{uint8_t}0x0266—1WCOTOB[7:0]
—WUPA[0] {uint8_t}0x0267—1WUP1A[7:0]
—WUPA[1] {uint8_t}0x0268—1WUP2A[7:0]
—WUPA[2] {uint8_t}0x0269—1WUP3A[7:0]
—WUPA[3] {uint8_t}0x026A—1WUP4A[7:0]
—WUPB[0] {uint8_t}0x026B—1WUP1B[7:0]
—WUPB[1] {uint8_t}0x026C—1WUP2B[7:0]
—WUPB[2] {uint8_t}0x026D—1WUP3B[7:0]
—WUPB[3] {uint8_t}0x026E—1WUP4B[7:0]
—WUPLA{uint8_t}0x026F—1——WUPLA[5:0]
—WUPLB{uint8_t}0x0270—1——WUPLB[5:0]
—WUPTA{uint8_t}0x0271—1———WUPTA[4:0]
—WUPTB{uint8_t}0x0272—1———WUPTB[4:0]
—RXCPA[0] {uint8_t}0x0273—1RXCPLA[7:0]
—RXCPA[1] {uint8_t}0x0274—1RXCPHA[7:0]
—RXCIA[0] {uint8_t}0x0275—1RXCILA[7:0]
—RXCIA[1] {uint8_t}0x0276—1RXCIHA[7:0]
—RXCSBA{uint8_t}0x0277—1RXCSBA[7:0]
—RXTLA[0] {uint8_t}0x0278—1RXTLLA[7:0]
—RXTLA[1] {uint8_t}0x0279—1————RXTLHA[3:0]
—RXCPB[0] {uint8_t}0x027A—1RXCPLB[7:0]
—RXCPB[1] {uint8_t}0x027B—1RXCPHB[7:0]
—RXCIB[0] {uint8_t}0x027C—1RXCILB[7:0]
—RXCIB[1] {uint8_t}0x027D—1RXCIHB[7:0]
—RXCSBB{uint8_t}0x027E——RXCSBB[7:0]
—RXTLB[0] {uint8_t}0x027F—1RXTLLB[7:0]
—RXTLB[1] {uint8_t}0x0280—1————RXTLHB[3:0]
—RXBC1{uint8_t}0x0281—1RXMSBBRXCBLB[1:0]RXCEBRXMSBA RXCBLA[1:0 ] RXCEA
—TMCR2A{uint8_t}0x0282—1—TMMSBTMSSETMPOLTMNRZE TMCRCL[1:0 ] TMCRE
—TMCR2B{uint8_t}0x0283—1—TMMSBTMSSETMPOLTMNRZE TMCRCL[1:0 ] TMCRE
—TMCSSA{uint8_t}0x0284—1TMSSHTMSSHL[2:0]TMSSP[3:0]
—TMCSSB{uint8_t}0x0285—1TMSSHTMSSHL[2:0]TMSSP[3:0]
—TMTLA[0] {uint8_t}0x0286—1TMTLL[7:0]
—TMTLA[1] {uint8_t}0x0287—1TMTLH[7:0]
—TMTLB[0] {uint8_t}0x0288—1TMTLL[7:0]
—TMTLB[1] {uint8_t}0x0289—1TMTLH[7:0]
—TMCPA[0] {uint8_t}0x028A—1TMCPL[7:0]
—TMCPA[1] {uint8_t}0x028B—1TMCPH[7:0]
—TMCPB[0] {uint8_t}0x028C—1TMCPL[7:0]
—TMCPB[1] {uint8_t}0x028D—1TMCPH[7:0]
—TMCIA[0] {uint8_t}0x028E—1TMCIL[7:0]
—TMCIA[1] {uint8_t}0x028F—1TMCIH[7:0]
—TMCIB[0] {uint8_t}0x0290—1TMCIL[7:0]
—TMCIB[1] {uint8_t}0x0291—1TMCIH[7:0]
—TMCSBA{uint8_t}0x0292—1TMCSB[7:0]
—TMCSBB{uint8_t}0x0293—1TMCSB[7:0]
—RSSC{uint8_t}0x0294—1—RSPKFRSHRXRSWLHRSUP[3:0]
Channel5————————
—FFREQ[0] {uint8_t}0x0295—1FFREQL[7:0]
—FFREQ[1] {uint8_t}0x0296—1FFREQM[7:0]
—FFREQ[2] {uint8_t}0x0297—1FFREQH[7:0]
—FEMS{uint8_t}0x0298—1PLLM[3:0]PLLS[3:0]
—FECR{uint8_t}0x0299—1——ANPSPLCKGADHSANDPS4N3LBNHB
flowCtrl {sSystemFlowCtrl}—5————————
—msmstate {uint8_t}0x029A—1SSM host state machine state to stop SW driven timeout control
—index {volatile uint8_t}0x029B—1Current SW state machine index
—pLut[2]{sysFlowStateMachineFuncLut}0x029C0x029D2Pointer to currently used SW state machine Look-up Table (low byte and high byte)
—lastStartedSsm {uint8_t}0x029E—1Indicates the last started SSM
*pRxSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x029F0x2A02Pointer to RX Buffered/Transparent SW state machine Look-up Table (low byte and high byte)
*pTxBufSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02A10x02A22Pointer to TX Buffered SW state machine Look-up Table (low byte and high byte)
*pTxTransSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02A30x02A42Pointer to TX Transparent SW state machine Look-up Table (low byte and high byte)
*pPollSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02A50x02A62Pointer to RX Polling SW state machine Look-up Table (low byte and high byte)
*pAntTuneSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02A70x02A82Pointer to Antenna Tuning SW state machine Look-up Table (low byte and high byte)
*pVcoCalSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02A90x02AA2Pointer to VCO tuning SW state machine Look-up Table (low byte and high byte)
reserved2————————
——0x02AB0x02AC2—
*pRssiSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02AD0x02AE2Pointer to RSSI SW state machine Look-up Table (low byte and high byte)
*pTempMeasSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02AF0x02B02Pointer to Temperature Measurement SW state machine Look-up Table (low byte and high byte)
*pSelfCheckSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02B10x02B22Pointer to selfCheck SW state machine Look-up Table (low byte and high byte)
*pSubChannelingSysFlowStateMachine {sysFlowStateMachineFuncLut} 2————————
——0x02B30x02B42Pointer to subChanneling SW state machine Look-up Table (low byte and high byte)
facLock {sFacLock}6————————
—confFEBIA{uint8_t}0x02B5—1SRAM copy of factory locked EEPROM variable
—confFEBT{uint8_t}0x02B6—1SRAM copy of factory locked EEPROM variable
—confFELNA{uint8_t}0x02B7—1SRAM copy of factory locked EEPROM variable
—confFELNA2{uint8_t}0x02B8—1SRAM copy of factory locked EEPROM variable
—confFETN4{uint8_t}0x02B9—1SRAM copy of factory locked EEPROM variable
—confFEVCOoffset{uint8_t}0x02BA—1SRAM copy of factory locked EEPROM variable
timer1 {sTmr1Config}5————————
—status{uint8_t}0x02BB—1LOCK———————
— compIsr[2] {timer1IRQHandler} 0x02BC0x02BD2Function pointer for timer1 compare interrupt (low byte and high byte)
— ovlsr[2] {timer1IRQHandler} 0x02BE0x02BF2Function pointer for timer1 overflow interrupt (low byte and high byte)
timer2 {sTmr2Config}5————————
—status{uint8_t}0x02C0—1LOCK———————
— compIsr[2] {timer2IRQHandler} 0x02C10x02C22Function pointer for timer2 compare interrupt (low byte and high byte)
— ovlsr[2] {timer2IRQHandler}] 0x02C30x02C42Function pointer for timer2 overflow interrupt (low byte and high byte)
timer3 {sTmr3Config}7——————
—status{uint8_t}0x02C5—1LOCK—————--
— compIsr[2] {timer3IRQHandler} 0x02C60x02C72Function pointer for timer3 compare interrupt (low byte and high byte)
— ovlsr[2] {timer3IRQHandler} 0x02C80x02C92Function pointer for timer3 overflow interrupt (low byte and high byte)
— capIsr[2] {timer3IRQHandler} 0x02CA0x02CB2Function pointer for timer3 capture interrupt (low byte and high byte)
timer4 {sTmr4Config}7——————
—status{uint8_t}0x02CC—1LOCK—————--
— compIsr[2] {timer4IRQHandler} 0x02CD0x02CE2Function pointer for timer4 compare interrupt (low byte and high byte)
— ovlsr[2] {timer4IRQHandler} 0x02CF0x02D02Function pointer for timer4 overflow interrupt (low byte and high byte)
— capIsr[2] {timer4IRQHandler} 0x02D10x02D22Function pointer for timer4 capture interrupt (low byte and high byte)
timer5 {sTmr5Config}5——————
—status{uint8_t}0x02D3—1LOCK—————--
— compIsr[2] {timer5IRQHandler} 0x02D40x02D52Function pointer for timer5 compare interrupt (low byte and high byte)
— ovlsr[2] {timer5IRQHandler} 0x02D60x02D72Function pointer for timer5 overflow interrupt (low byte and high byte)
calib {sCalibResults}7————————
—sramFEAT {uint8_t}0x02D8—1————ANTN[3:0]
—sramTEMPH0x02D9—1Temperature high byte
—sramTEMPL0x02DA—1Temperature low byte
—tempMeas0x02DB—18-bit temperature measurement result (Range 0..175)
—srcRes {uint8_t}0x02DC—1Result of the measured f_src oscillator
—srcCorVal0x02DD—1Correction value for timer 1
—vcoRes {uint8_t}0x02DE—1Result of the measured f_vco oscillator
trxConf {sTrxConfig}10————————
— tuneCheckConfig {tuneCheckConfig_t} 0x02DF—1EN_ANT_TUNEEN_TEMP_ MEASEN_SRCCALEN_FRCCALEN_VCOCALEN_RFCALEN_SELFCHECKEN_REGREFRESH
— systemModeConfig {sysModeConfig_t} 0x02E0—1RF_CALANT_TUNEVCO_TUNEIDLEModeselectionDIRECT/ NORMALTMDENOPM[1:0]
— serviceChannelConfig {svcChConfig_t} 0x02E1—1enaPathBenaPathACh[1:0]-Ser[2:0]
— systemConfig{uint8_t} 0x02E2 — 1 —— SRCAO FRCAO SFIFO_OFL_UFL_RX_ DISABLE DFIFO_OFL_UFL_RX_ DISABLE currentIdleModeSelector VS5V
—serviceInitConfig{uint8_t}0x02E3—1UPDATE_FLAG————eepromService[1:0]sramService
—miscTrigger{uint8_t}0x02E4—1——————Pc4oldStatestartRssiMeas
— lastSystemModeConfig {sysModeConfig_t} 0x02E5—1RF_CALANT_TUNEVCO_TUNEIDLEModeselectionDIRECT/ NORMALTMDENOPM[1:0]
— lastServiceChannelConfig {svcChConfig_t} 0x02E6 — 1 enaPathB enaPathA Ch[1:0] — Ser[2:0]
—idScanStatus{volatile uint8_t}0x02E7—1 IDscan_result IDscan_valid IDscan_BufFull IDena[4:0]
—idScanCtrl{volatile uint8_t}0x02E8—1 IDscan_active IDscan_EOTB IDscan_EOTA IDcnt[4:0]
tmpAryApp10————————
—tmpAryApp[10] {uint8_t}0x02E90x02F210Temporary array
sleepModeConfig1————————
— sleepModeConfig {uint8_t} 0x02F3 — 1 Firmware SleepMode Enable——— sleepMode[2:0] —
rfPaCtrl {sRfPaCtrl}——1————————
—paDamping {uint8_t}0x02F4—1Damping of the EEPROM configured output power
frcResults {sFrcCalib}——3————————
—highByte0x02F5—18q8 representation highByte.lowByte
—lowByte0x02F6—18q8 representation highByte.lowByte
—compValData0x02F7—1Timer3 icap result during the tuning process
extReq {sExtReq}—5————————
— tuneCheckConfig {tuneCheckConfig_t} 0x02F8—1EN_ANT_TUNEEN_TEMP_MEASEN_SRCCALEN_FRCCALEN_VCOCALEN_RFCALEN_SELFCHECKEN_REGREFRESH
— systemModeConfig {sysModeConfig_t} 0x02F9—1RF_CALANT_TUNEVCO_TUNEIDLEModeSelectorDIRECT/ NORMALTMDENOPM[1:0]
— serviceChannelConfig {svcChConfig_t} 0x02FA—1enaPathBenaPathACh[1:0]—Ser[2:0]
—serviceInitConfig{uint8_t}0x02FB—1updateFlag————eepromService[1:0]sramService
—miscTrigger{uint8_t}0x02FC—1———————StartRssiMeas
customCmd {sCustomCommand} —2————————
—flashFunc[2]{customPtr}0x02FD0x02FE1Pointer to a function in flash used to add/patch the SPI (high byte and low byte)
triggerEEPwr {sTriggerEEP} ——3————————
—triggerEEPwr{uint8_t}0x02FF—1Needed to trigger the EEPsecureWrite
debug {sDebug}——2————————
—errorCode{uint8_t}0x0300—1Contains the error information of last system error
—ssmErrorCode{uint8_t}0x0301—1Contains the detailed error information of SSM error
pollConfig {sPollingConfig}—34————————
—confT1COR{uint8_t}0x0302—1T1COR[7:0]
—confT1MR{uint8_t}0x0303—1T1MR[7:0]
— pollChanConf[0].config {sPollingChannelConfig} 0x0304—1RfCalib—VCO_TUNE———EOLEOP
— pollChanConf[0].svChanConfig {sPollingChannelConfig} 0x0305 — 1 enaPathB enaPathA Ch[1:0] — Ser[2:0]
—…———————————
— pollChanConf[15].config {sPollingChannelConfig} 0x0322—1RfCalib—VCO_TUNE———EOLEOP
— pollChanConf[15].svChanConfig {sPollingChannelConfig} 0x0323 — 1 enaPathB enaPathA Ch[1:0] — Ser[2:0]
pollStatus {sPollingStatus}—4————————
—cycleCnt{uint16_t}0x03240x03252Global 16bit polling cycle counter (low byte and high byte)
—confIdx{uint8_t}0x0326—1Currently used polling configuration counter
—flags{uint8_t}0x0327—1———VCOcalibOnFirstChannelSelfCheckAfterFirstCycleSelfCheckFastPollingPollingActive
sramServices[NUM_SRAM_SERVICES] {sServiceConfiguration} 2 x 126————————
—CHCR{uint8_t} 0x0328 0x03B5 —1————BWM[3:0]
—CHDN{uint8_t} 0x0329 0x03B6 —1——ADCDNBBDN[4:0]
— CHSTARTFILTER {uint8_t} 0x032A 0x03B7 —1——PLDTHADTDFDTFID[2:0]
—DMCDA{uint8_t} 0x032B 0x03B8 —1DMCTA[2:0]DMCLA[4:0]
—DMCDB{uint8_t} 0x032C 0x03B9 —1DMCTB[2:0]DMCLB[4:0]
—DMCRA{uint8_t} 0x032D 0x03BA —1DMARASY1TASASKADMPGA[4:0]
—DMCRB{uint8_t} 0x032E 0x03BB —1DMARBSY1TBSASKBDMPGB[4:0]
—DMDRA{uint8_t} 0x032F 0x03BC —1DMDNA[3:0]DMAA[3:0]
—DMDRB{uint8_t} 0x0330 0x03BD —1DMDNB[3:0]DMAB[3:0]
—DMMA{uint8_t} 0x0331 0x03BE —1DMNEADMHADMPADMATA[4:0]
—DMMB{uint8_t} 0x0332 0x03BF —1DMNEBDMHBDMPBDMATB[4:0]
—EOT1A{uint8_t} 0x0333 0x03C0 —1EOTBFERRFEATELREATMOFEAMANFEASYTFEAAMPFEACARFEA
—EOT1B{uint8_t} 0x0334 0x03C1 —1EOTAFERRFEBTELREBTMOFEBMANFEBSYTFEBAMPFEBCARFEB
—EOT2A{uint8_t} 0x0335 0x03C2 —1EOTBFERRFEATELREATMOFEAMANFEASYTFEAAMPFEACARFEA
—EOT2B{uint8_t} 0x0336 0x03C3 —1EOTAFERRFEBTELREBTMOFEBMANFEBSYTFEBAMPFEBCARFEB
—EOT3A{uint8_t} 0x0337 0x03C4 —1EOTBFERRFEATELREATMOFEAMANFEASYTFEAAMPFEACARFEA
—EOT3B{uint8_t} 0x0338 0x03C5 —1EOTAFERRFEBTELREBTMOFEBMANFEBSYTFEBAMPFEBCARFEB
—FEALR_FEANT{uint8_t} 0x0339 0x03C6 —1——FEALR.RNGE[1:0]FEANT.LVLC[3:0]
—FEAT{uint8_t} 0x033A 0x03C7 —1————ANTN[3:0]
—FEPAC{uint8_t} 0x033B 0x03C8 —1PACR[7:0]
—FEVCO{uint8_t} 0x033C 0x03C9 —1VCOB[3:0]CPCC[3:0]
—FEVCT{uint8_t} 0x033D 0x03CA —1————FEVCT[3:0]
—FREQoffset[0] {uint8_t} 0x033E 0x03CB —1FREQoffset[7:0]
—FREQoffset[1] {uint8_t} 0x033F 0x03CC —1FREQoffset [15:8]
—txDevA[0] {uint8_t} 0x0340 0x03CD —1txDevA[7:0]
—txDevA[1] {uint8_t} 0x0341 0x03CE —1txDevA[15:8]
—txDevB[0] {uint8_t} 0x0342 0x03CF —1txDevB[7:0]
—txDevB[1] {uint8_t} 0x0343 0x03D0 —1txDevB[15:8]
—GACDIVA[0] {uint8_t} 0x0344 0x03D1 —1GACDIVL[7:0]
—GACDIVA[1] {uint8_t} 0x0345 0x03D2 —1———GACDIVH[4:0]
—GACDIVB[0] {uint8_t} 0x0346 0x03D3 —1GACDIVL[7:0]
—GACDIVB[1] {uint8_t} 0x0347 0x03D4 —1———GACDIVH[4:0]
—IF[0] {uint8_t} 0x0348 0x03D5 —1IF[7:0]
—IF[1] {uint8_t} 0x0349 0x03D6 —1IF[15:8]
—RDOCR{uint8_t} 0x034A 0x03D7 —1———ETRPBETRPATMDS[1:0]—
—rssiSysConf{uint8_t} 0x034B 0x03D8 —1RssiEnable—rssiBufEvMaskRSSIbuf[4:0]
—rxSetPathA[0] {uint8_t} 0x034C 0x03D9 —1—rxBufEvMaskARXbufA[5:0]
—rxSetPathA[1] {uint8_t} 0x034D 0x03DA —1IWUPADARAGAPMARXETHA———RXMODA
—rxSetPathB[0] {uint8_t} 0x034E 0x03DB —1—rxBufEvMaskBRXbufB[5:0]
—rxSetPathB[1] {uint8_t} 0x034F 0x03DC —1IWUPBDARBGAPMBRXETHB———RXMODB
—rxSysEvent{uint8_t} 0x0350 0x03DD —1 IDCHKA_Mask WCOKA_Mask SOTA_Mask EOTA_Mask IDCHKB_Mask WCOKB_Mask SOTB_Mask EOTB_Mask
—rxSysSet{uint8_t} 0x0351 0x03DE —1subChanneling_ENAIdScan_ENAIFAmplifier_ENAPathValidAfterSOT_ENAAntDampPathB_disableAntDampPathA_disable Switching_SDTX Switching_SDRX
—SFIDA[0] {uint8_t} 0x0352 0x03DF —1SFID1A[7:0]
—SFIDA[1] {uint8_t} 0x0353 0x03E0 —1SFID2A[7:0]
—SFIDA[2] {uint8_t} 0x0354 0x03E1 —1SFID3A[7:0]
—SFIDA[3] {uint8_t} 0x0355 0x03E2 —1SFID4A[7:0]
—SFIDB[0] {uint8_t} 0x0356 0x03E3 —1SFID1B[7:0]
—SFIDB[1] {uint8_t} 0x0357 0x03E4 —1SFID2B[7:0]
—SFIDB[2] {uint8_t} 0x0358 0x03E5 —1SFID3B[7:0]
—SFIDB[3] {uint8_t} 0x0359 0x03E6 —1SFID4B[7:0]
—SFIDCA{uint8_t} 0x035A 0x03E7 —1SEMEA——SFIDTA[4:0]
—SFIDCB{uint8_t} 0x035B 0x03E8 —1SEMEB——SFIDTB[4:0]
—SFIDLA{uint8_t} 0x035C 0x03E9 —1——SFIDLA[5:0]
—SFIDLB{uint8_t} 0x035D 0x03EA —1——SFIDLB[5:0]
—SOT1A{uint8_t} 0x035E 0x03EB —1WCOBOERROEASFIDEAWUPEAMANOEASYTOEAAMPOEACAROEA
—SOT1B{uint8_t} 0x035F 0x03EC —1WCOAOERROEBSFIDEBWUPEBMANOEBSYTOEBAMPOEBCAROEB
—SOT2A{uint8_t} 0x0360 0x03ED —1WCOBOERROEASFIDEAWUPEAMANOEASYTOEAAMPOEACAROEA
—SOT2B{uint8_t} 0x0361 0x03EE —1WCOAOERROEBSFIDEBWUPEBMANOEBSYTOEBAMPOEBCAROEB
—SOTtimeOutA{uint8_t} 0x0362 0x03EF —1SOTTOA[7:0]
—SOTtimeOutB{uint8_t} 0x0363 0x03F0 —1SOTTOB[7:0]
—SYCA{uint8_t} 0x0364 0x03F1 —1SYTLA[3:0]SYCSA[3:0]
—SYCB{uint8_t} 0x0365 0x03F2 —1SYTLB[3:0]SYCSB[3:0]
—FSFCRA{uint8_t} 0x0366 0x03F3 —1ASDIV[3:0]——BTSEL[1:0]
—FSFCRB{uint8_t} 0x0367 0x03F4 —1ASDIV[3:0]——BTSEL[1:0]
—TMUL{uint8_t} 0x0368 0x03F5 —1TMUL[7:0]
—trxSysConf{uint8_t} 0x0369 0x03F6 —1————TRPB_ENATRPA_ENAAntennaSwitching_ENAChannelSwitch_ENA
—TXDRA[0] {uint8_t} 0x036A 0x03F7 —1TXDRA[7:0]
—TXDRA[1] {uint8_t} 0x036B 0x03F8 —1TXDRA[15:8]
—TXDRB[0] {uint8_t} 0x036C 0x03F9 —1TXDRB[7:0]
—TXDRB[1] {uint8_t} 0x036D 0x03FA —1TXDRB[15:8]
—txSetPathA[0] {uint8_t} 0x036E 0x03FB —1GAUSPREEStartTxFillLevelA[5:0]
—txSetPathA[1] {uint8_t} 0x036F 0x03FC —1TXMODAASKshapingenable—StartPreambleFillLevelA[4:0]
—txSetPathB[0] {uint8_t} 0x0370 0x03FD —1GAUSPREEStartTxFillLevelB[5:0]
—txSetPathB[1] {uint8_t} 0x0371 0x03FE —1TXMODBASKshapingenable—StartPreambleFillLevelB[4:0]
—txSysEventA{uint8_t} 0x0372 0x03FF —1TX_EndingtxBufEvMaskATxBufFillLevelA[5:0]
—txSysEventB{uint8_t} 0x0373 0x0400 —1TX_EndingtxBufEvMaskBTxBufFillLevelB[5:0]
— txPreambleSysEventA {uint8_t} 0x0374 0x0401 —1——txPreambleBufEv MaskAPreambleBufFillLevelA[4:0]
— txPreambleSysEventB {uint8_t} 0x0375 0x0402 —1——txPreambleBufEv MaskBPreambleBufFillLevelB[4:0]
—WCOtimeOutA{uint8_t} 0x0376 0x0403 —1WCOTOA[7:0]
—WCOtimeOutB{uint8_t} 0x0377 0x0404 —1WCOTOB[7:0]
—WUPA[0] {uint8_t} 0x0378 0x0405 —1WUP1A[7:0]
—WUPA[1] {uint8_t} 0x0379 0x0406 —1WUP2A[7:0]
—WUPA[2] {uint8_t} 0x037A 0x0407 —1WUP3A[7:0]
—WUPA[3] {uint8_t} 0x037B 0x0408 —1WUP4A[7:0]
—WUPB[0] {uint8_t} 0x037C 0x0409 —1WUP1B[7:0]
—WUPB[1] {uint8_t} 0x037D 0x040A —1WUP2B[7:0]
—WUPB[2] {uint8_t} 0x037E 0x040B —1WUP3B[7:0]
—WUPB[3] {uint8_t} 0x037F 0x040C —1WUP4B[7:0]
—WUPLA{uint8_t} 0x0380 0x040D —1——WUPLA[5:0]
—WUPLB{uint8_t} 0x0381 0x040E —1——WUPLB[5:0]
—WUPTA{uint8_t} 0x0382 0x040F —1———WUPTA[4:0]
—WUPTB{uint8_t} 0x0383 0x0410 —1———WUPTB[4:0]
—RXCPA[0] {uint8_t} 0x0384 0x0411 —1RXCPLA[7:0]
—RXCPA[1] {uint8_t} 0x0385 0x0412 —1RXCPHA[7:0]
—RXCIA[0] {uint8_t} 0x0386 0x0413 —1RXCILA[7:0]
—RXCIA[1] {uint8_t} 0x0387 0x0414 —1RXCIHA[7:0]
—RXCSBA{uint8_t} 0x0388 0x0415 —1RXCSBA[7:0]
—RXTLA[0] {uint8_t} 0x0389 0x0416 —1RXTLLA[7:0]
—RXTLA[1] {uint8_t} 0x038A 0x0417 —1————RXTLHA[3:0]
—RXCPB[0] {uint8_t} 0x038B 0x0418 —1RXCPLB[7:0]
—RXCPB[1] {uint8_t} 0x038C 0x0419 —1RXCPHB[7:0]
—RXCIB[0] {uint8_t} 0x038D 0x041A —1RXCILB[7:0]
—RXCIB[1] {uint8_t} 0x038E 0x041B —1RXCIHB[7:0]
—RXCSBB{uint8_t} 0x038F 0x041C —1RXCSBB[7:0]
—RXTLB[0] {uint8_t} 0x0390 0x041D —1RXTLLB[7:0]
—RXTLB[1] {uint8_t} 0x0391 0x041E —1————RXTLHB[3:0]
—RXBC1{uint8_t} 0x0392 0x041F —1RXMSBBRXCBLB[1:0]RXCEBRXMSBARXCBLA[1:0]RXCEA
—TMCR2A{uint8_t} 0x0393 0x0420 —1—TMMSBTMSSETMPOLTMNRZETMCRCL[1:0]TMCRE
—TMCR2B{uint8_t} 0x0394 0x0421 —1—TMMSBTMSSETMPOLTMNRZETMCRCL[1:0]TMCRE
—TMCSSA{uint8_t} 0x0395 0x0422 —1TMSSHTMSSHL[2:0]TMSSP[3:0]
—TMCSSB{uint8_t} 0x0396 0x0423 —1TMSSHTMSSHL[2:0]TMSSP[3:0]
—TMTLA[0] {uint8_t} 0x0397 0x0424 —1TMTLL[7:0]
—TMTLA[1] {uint8_t} 0x0398 0x0425 —1TMTLH[7:0]
—TMTLB[0] {uint8_t} 0x0399 0x0426 —1TMTLL[7:0]
—TMTLB[1] {uint8_t} 0x039A 0x0427 —1TMTLH[7:0]
—TMCPA[0] {uint8_t} 0x039B 0x0428 —1TMCPL[7:0]
—TMCPA[1] {uint8_t} 0x039C 0x0429 —1TMCPH[7:0]
—TMCPB[0] {uint8_t} 0x039D 0x042A —1TMCPL[7:0]
—TMCPB[1] {uint8_t} 0x039E 0x042B —1TMCPH[7:0]
—TMCIA[0] {uint8_t} 0x039F 0x042C —1TMCIL[7:0]
—TMCIA[1] {uint8_t} 0x03A0 0x042D —1TMCIH[7:0]
—TMCIB[0] {uint8_t} 0x03A1 0x042E —1TMCIL[7:0]
—TMCIB[1] {uint8_t} 0x03A2 0x042F —1TMCIH[7:0]
—TMCSBA{uint8_t} 0x03A3 0x0430 —1TMCSB[7:0]
—TMCSBB{uint8_t} 0x03A4 0x0431 —1TMCSB[7:0]
—RSSC{uint8_t} 0x03A5 0x0432 —1—RSPKFRSHRXRSWLHRSUP[3:0]
Channel[0]—2 x 5————————
—FFREQ[0] {uint8_t} 0x03A6 0x0433 —1FFREQL[7:0]
—FFREQ[1] {uint8_t} 0x03A7 0x0434 —1FFREQM[7:0]
—FFREQ[2] {uint8_t} 0x03A8 0x0435 —1FFREQH[7:0]
—FEMS{uint8_t} 0x03A9 0x0436 —1PLLM[3:0]PLLS[3:0]
—FECR{uint8_t} 0x03AA 0x0437 —1——ANPSPLCKGADHSANDPS4N3LBNHB
Channel[1]—2 x 5————————
—FFREQ[0] {uint8_t} 0x03AB 0x0438 —1FFREQL[7:0]
—FFREQ[1] {uint8_t} 0x03AC 0x0439 —1FFREQM[7:0]
—FFREQ[2] {uint8_t} 0x03AD 0x043A —1FFREQH[7:0]
—FEMS{uint8_t} 0x03AE 0x043B —1PLLM[3:0]PLLS[3:0]
—FECR{uint8_t} 0x03AF 0x043C —1——ANPSPLCKGADHSANDPS4N3LBNHB
Channel[2]—2 x 5————————
—FFREQ[0] {uint8_t} 0x03B0 0x043D —1FFREQL[7:0]
—FFREQ[1] {uint8_t} 0x03B1 0x043E —1FFREQM[7:0]
—FFREQ[2] {uint8_t} 0x03B2 0x043F —1FFREQH[7:0]
—FEMS{uint8_t} 0x03B3 0x0440 —1PLLM[3:0]PLLS[3:0]
—FECR{uint8_t} 0x03B4 0x0441 —1——ANPSPLCKGADHSANDPS4N3LBNHB
rfRssi——30————————
— rssiThreshold[0][0].RSSL {uint8_t} 0x0442 — 1 RSSI low threshold for service 0 and channel 0
— rssiThreshold[0][0].RSSH {uint8_t} 0x0443—1RSSI high threshold for service 0 and channel 0
— rssiThreshold[0][1].RSSL {uint8_t} 0x0444 — 1 RSSI low threshold for service 0 and channel 1
— rssiThreshold[0][1].RSSH {uint8_t} 0x0445—1RSSI high threshold for service 0 and channel 1
—...———
— rssiThreshold[4][2].RSSH {uint8_t} 0x045F—1RSSI high threshold for service 4 and channel 2
— rssiAtWcok[0][0] {uint8_t} 0x0460—1rssiAtWcok for service 0 and channel 0
— rssiAtWcok[0][1] {uint8_t} 0x0461—1rssiAtWcok for service 0 and channel 1
— rssiAtWcok[0][2] {uint8_t} 0x0462—1rssiAtWcok for service 0 and channel 2
— rssiAtWcok[1][0] {uint8_t} 0x0463—1rssiAtWcok for service 1 and channel 0
—…———
— rssiAtWcok[4][2] {uint8_t} 0x046E—1rssiAtWcok for service 4 and channel 2
frequencyOffsetAtWcok—1————————
— frequencyOffsetAtWcok {uint8_t} 0x046F—1Contains the detected frequency offset at WCOK
subChan {sSubChanneling}—4————————
—rssi[0]{uint8_t}0x0470—1First measured RSSI value on center frequency
—rssi[1] {uint8_t}0x0471—1First measured RSSI value on lower frequency
—rssi[2] {uint8_t}0x0472—1First measured RSSI value on upper frequency
—flags{uint8_t}0x0473—1———————FillLevel reached
rxIrqEvents[3]{uint8_t}—3————————
—rxIrqEvents[0] {uint8_t}0x0474—1RDSIMR configuration before WCOA/B
—rxIrqEvents [1] {uint8_t}0x0475—1RDSIMR configuration after WCOA/B
—rxIrqEvents [2] {uint8_t}0x0476—1RDSIMR configuration after SOTA/B
sramServiceChannelSwitchConfig [NUM_SRAM_SERVICES] {sEEPromServiceChannelSwitchConfig_t} 4 ————————
—sramServiceChannelSwitchConfig [0]. antennaSwitchingMask 0x0477 — 1 Parameter antennaSwitchingMask for Channel Switch configuration for service 3 (SRAM)
—sramServiceChannelSwitchConfig [0]. antennaSwitchingPattern 0x0478 — 1 Parameter antennaSwitchingPattern for Channel Switch configuration for service 3 (SRAM)
—sramServiceChannelSwitchConfig [1]. antennaSwitchingMask 0x0479 — 1 Parameter antennaSwitchingMask for Channel Switch configuration for service 4 (SRAM)
—sramServiceChannelSwitchConfig [1]. antennaSwitchingPattern 0x047A — 1 Parameter antennaSwitchingPattern for Channel Switch configuration for service 4 (SRAM)
sramPollingChannelStatistics {sSramPollingChannelStatistics} —5————————
—sramPollingChannelStatistics {uint8_t}0x047B—1Contains the polling channel index of the best channel
—sramPollingChannelStatistics {uint8_t}0x047C—1Contains the service and channel number of the best channel
—LowestRssiOfCurPolCycle0x047D—1Temporary RSSI value for best channel feature
—tempBestChannelPollingIndex0x047E—1Temporary Index value for best channel feature
—tempBestChannelServiceChannelConfig0x047F—1Temporary config value for best channel feature