27.4.1 ADCON0
Note:
- Only available on 40/44-pin devices (PIC16F15274/75/76).
| Name: | ADCON0 |
| Offset: | 0x09D |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHS[5:0] | GO | ON | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W/HS/HC | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:2 – CHS[5:0] Analog Channel Select
| CHS | Selected Channel |
|---|---|
111111-100110 | Reserved |
100101 | FVR Buffer 1 |
100100 | VSS |
100011 | Reserved |
100010 | RE2(1) |
100001 | RE1(1) |
100000 | RE0(1) |
011111 | RD7(1) |
011110 | RD6(1) |
011101 | RD5(1) |
011100 | RD4(1) |
011011 | RD3(1) |
011010 | RD2(1) |
011001 | RD1(1) |
011000 | RD0(1) |
010111 | RC7 |
010110 | RC6 |
010101 | RC5 |
010100 | RC4 |
010011 | RC3 |
010010 | RC2 |
010001-001110 | Reserved |
001101 | RB5 |
001100 | RB4 |
001011 | RB3 |
001010 | RB2 |
001001 | RB1 |
001000 | RB0 |
000111 | Reserved |
000110 | Reserved |
000101 | RA5 |
000100 | Reserved |
000011 | RA3 |
000010 | RA2 |
000001 | RA1 |
000000 | RA0 |
Bit 1 – GO ADC Conversion Status
| Value | Description |
|---|---|
| 1 | ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. |
| 0 | ADC conversion completed/not in progress |
Bit 0 – ON ADC Enable
| Value | Description |
|---|---|
| 1 | ADC is enabled |
| 0 | ADC is disabled an consumes no operating current |