32.4.6 Analog-to-Digital Converter (ADC) Conversion Timing Specifications

Table 32-14.
Standard Operating Conditions (unless otherwise stated)
Param No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
AD20	T_AD	ADC Clock Period	0.5	—	9	μs	F_OSC clock source
AD21	T_AD	ADC Clock Period	1	2	6	μs	ADCRC clock source
AD22	T_CNV	Conversion Time	—	11	—	T_AD	Set of GO bit to clear of GO bit
AD23	T_ACQ	Acquisition Time	—	2	—	μs
AD24	T_HCD	Sample and Hold Capacitor Disconnect Time	—	—	—	—	F_OSC clock source
* - These parameters are characterized but not tested. † Data in ‘Typ’ column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Figure 32-9. ADC Conversion Timing (ADC Clock F_OSC-Based)

Figure 32-10. ADC Conversion Timing (ADC Clock from ADCRC)

Note:

If the ADC clock source is selected as F_RC, a time of T_CY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.

PIC16F15256/74/75/76