24.1.2.9 9-Bit Address Detection Mode Setup

This mode is typically used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable, follow these steps:

  1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see EUSART Baud Rate Generator (BRG)).
  2. Set the RXxPPS register to select the RXx input pin.
  3. Clear the ANSEL bit for the RXx pin (if applicable).
  4. Enable the serial port by setting the SPEN bit. The SYNC bit must be cleared for asynchronous operation.
  5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register.
  6. Enable 9-bit reception by setting the RX9 bit.
  7. Enable address detection by setting the ADDEN bit.
  8. Enable reception by setting the CREN bit.
  9. The RCxIF Interrupt Flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit is also set.
  10. Read the RCxSTA register to get the Error flags. The ninth data bit will always be set.
  11. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device’s address.
  12. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.
  13. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.
Figure 24-5. Asynchronous Reception