6.72.1 Description
Loads one byte pointed to by the Z-register into the destination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (ZLSb == 0) or high byte (ZLSb == 1). This instruction can address the first 64 KB (32K words) of program memory. The Z-Pointer Register can either be left unchanged by the operation, or it can be incremented. The incrementation does not apply to the RAMPZ Register.
Devices with self-programming capability can use the LPM instruction to read the Fuse and Lock bit values. Refer to the device documentation for a detailed description.
The LPM instruction is not available on all devices. Refer to Appendix A.
The result of these combinations is undefined:
LPM r30, Z+
LPM r31, Z+
|
Operation: |
Comment: | ||
|
(i) |
R0 ← PS(Z) |
Z: Unchanged, R0 implied destination register | |
|
(ii) |
Rd ← PS(Z) |
Z: Unchanged | |
|
(iii) |
Rd ← PS(Z) Z ← Z + 1 |
Z: Post incremented | |
|
Syntax: |
Operands: |
Program Counter: | |
|
(i) |
LPM |
None, R0 implied |
PC ← PC + 1 |
|
(ii) |
LPM Rd, Z |
0 ≤ d ≤ 31 |
PC ← PC + 1 |
|
(iii) |
LPM Rd, Z+ |
0 ≤ d ≤ 31 |
PC ← PC + 1 |
16-bit Opcode:
| (i) | 1001 | 0101 | 1100 | 1000 |
| (ii) | 1001 | 000d | dddd | 0100 |
| (iii) | 1001 | 000d | dddd | 0101 |