6.53.1 Description
Loads one byte pointed to by the Z-register and the RAMPZ Register in the I/O space, and places this byte in the destination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (ZLSB == 0) or high byte (ZLSB == 1). This instruction can address the entire program memory space. The Z-Pointer Register can either be left unchanged by the operation, or it can be incremented. The incrementation applies to the entire 24-bit concatenation of the RAMPZ and Z-Pointer Registers.
Devices with self-programming capability can use the ELPM instruction to read the Fuse and Lock bit value. Refer to the device documentation for a detailed description.
This instruction is not available on all devices. Refer to Appendix A.
The result of these combinations is undefined:
ELPM r30, Z+
ELPM r31, Z+
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Operation: |
Comment: | ||
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(i) |
R0 ← PS(RAMPZ:Z) |
RAMPZ:Z: Unchanged, R0 implied destination register | |
|
(ii) |
Rd ← PS(RAMPZ:Z) |
RAMPZ:Z: Unchanged | |
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(iii) |
Rd ← PS(RAMPZ:Z) |
(RAMPZ:Z) ← (RAMPZ:Z) + 1 RAMPZ:Z: Post incremented | |
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Syntax: |
Operands: |
Program Counter: | |
|
(i) |
ELPM |
None, R0 implied |
PC ← PC + 1 |
|
(ii) |
ELPM Rd, Z |
0 ≤ d ≤ 31 |
PC ← PC + 1 |
|
(iii) |
ELPM Rd, Z+ |
0 ≤ d ≤ 31 |
PC ← PC + 1 |
16 bit Opcode:
| (i) | 1001 | 0101 | 1101 | 1000 |
| (ii) | 1001 | 000d | dddd | 0110 |
| (iii) | 1001 | 000d | dddd | 0111 |