6.41.1 Description
Clears the T bit in SREG (Status Register). (Equivalent to instruction BCLR 6.)
|
Operation: | |||
|
(i) |
T ← 0 | ||
|
Syntax: |
Operands: |
Program Counter: | |
|
(i) |
CLT |
None |
PC ← PC + 1 |
16-bit Opcode:
| 1001 | 0100 | 1110 | 1000 |