6.79.2 Status Register (SREG) and Boolean Formula

ITHSVNZC
C
R15
Z

R15R14R13R12R11R10R9R8R7R6R5R4R3R2R1R0

Set if the result is 0x0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

;******************************************************************************
;* DESCRIPTION
;* Signed multiply of two 16-bit numbers with 32-bit result.
;* USAGE
;* r19:r18:r17:r16 = r23:r22 * r21:r20
;******************************************************************************
muls16x16_32:
      clr   r2
      muls  r23, r21      ; (signed)ah * (signed)bh
      movw  r18, r0
      mul   r22, r20      ; al * bl
      movw  r16, r0
      mulsu r23, r20      ; (signed)ah * bl
      sbc   r19, r2
      add   r17, r0
      adc   r18, r1
      adc   r19, r2
      mulsu r21, r22      ; (signed)bh * al
      sbc   r19, r2
      add   r17, r0
      adc   r18, r1
      adc   r19, r2
      ret
Words
1 (2 bytes)
Table 6-79. Cycles
NameCycles
AVRe2
AVRxm2
AVRxt2
AVRrcN/A