1.13 Error Detection and Recovery
The I3C Target module supports various error detection and recovery methods specified in the MIPI I3C Specification.
Table 1-3 summarizes the various supported methods.
| Error Type | Description | Detection | Recovery |
|---|---|---|---|
| TE0 | Invalid Broadcast Address | Invalid combination of 7’h7E/W; TE0ERR/BUSEIF bits
set | Target ignores all traffic on the bus and waits for an HDR Exit Pattern |
| TE1 | Invalid CCC Code | Invalid parity after CCC code; TE1ERR/BUSEIF bits set | |
| TE2 | Invalid Write Data | Invalid parity after Private/CCC Write data byte; TE2ERR/BUSEIF bits set | Target waits for the next Stop or Restart |
| TE3 | Invalid Assigned Address during Dynamic Address Assignment | Invalid parity after assigned Dynamic Address; TE3ERR/BUSEIF bits set | Target NACKs and waits for next Restart to participate in Dynamic Address Assignment again |
| TE4 | Illegally formatted data during Dynamic Address Assignment | Invalid 7’h7E/R after Restart; TE4ERR/BUSEIF bits
set | Target NACKs and waits for next Stop |
| TE5 | Illegally formatted CCC frame | Monitor CCC frame for any discrepancy; TE5ERR/BUSEIF bits set | Target NACKs and waits for next Stop or Restart |
| TE6 | Corrupted R/W bit during Private Transfer | Monitor data on SDA line during Private Read; TE6ERR/BUSEIF bits set | Target lets go of the bus and waits for next Stop or Restart |