1.2 SDA/SCL Pad Control
The I3C module can be connected to a pure or mixed I3C bus using dedicated SDA and SCL pins. Refer to the device data sheet for the location of I3C compatible SDA/SCL pads.
The I3C SDA and SCL pads are located in a separate Multi-Voltage I/O (MVIO) power domain and are powered by a separate VDDIOx power pin. The VDDIOx power pin should be connected to the same voltage as the desired I3C bus voltage on the SDA and SCL pins. This is because the device will drive the SDA line at the VDDIOx voltage level in push-pull mode during I3C read transactions. The individual SDA and SCL pins are designed to be fail-safe and high voltage input tolerant, meaning the device will not source or sink leakage current should the bus voltage become higher or lower than the VDDIOx power pin.
The following selections must be made for the I3C module to operate properly:
- MVIO Operating Mode: The VDDIOxMD configuration bit must be set properly based on the VDDIOx power level. Select the Standard Operating Range for VDDIOxMD if VDDIOx is in the 1.62V-3.63V range. Select the Low-voltage Operating Range for VDDIOxMD if VDDIOx is in the 0.95V-1.62V range. Refer to the device data sheet for additional VDD requirements when operating in the Low-voltage range.
- Open-Drain Inputs: The individual SDA and SCL pins must be configured as open-drain inputs using the Open-Drain Control (ODCONx) and Tri-State Control (TRISx) registers
- Input Buffer Selection: An appropriate input buffer must be selected for the I3C module using the I3CBUF bits in the RxyFEAT register. It must be noted that not all input buffers are operational at all voltage levels. It is recommended to use the I3C Fast ST Buffer when MVIO is operating in Standard range and the I3C Low-voltage Buffer when MVIO is operating in Low-voltage range.