1.8 Legacy I²C Transaction

The module participates in a Legacy I²C Transaction anytime it does not have a Dynamic Address assigned and is not operating in Static Address SDR mode. The controller can begin an I²C Transaction with the Target by addressing it directly using the Static Address after a Start/Restart. When a Static Address match occurs, the SADRIF bit is set, and the RNW bits are changed to reflect whether the transaction is a read or write request from the controller.

As a Private I3C Write transaction, the Target’s ACK/NACK response to an I²C Write request depends on the settings of the ACKPW and ACKPWOS bits. Once the I²C Write request is ACK’d, the controller sends an 8-bit data byte on the bus, and the Target responds with an ACK if data can be received in the Receive FIFO. The data are received in the Receive FIFO, which becomes available to be read from the I3CxRXB register.

Just like a Private I3C Read transaction, the Target’s ACK/NACK response to an I²C Read request depends on the status of Transmit FIFO. Once the I²C Read request is ACK’d, the Target starts sending the 8-bit data byte on the bus, and the controller responds with an ACK/NACK, and the appropriate I2CACKIF/I2CNACKIF flags are set in the module.

All the flags and command bits for buffer management, as mentioned in the Private I3C Transaction section, are also available in the Legacy I²C mode. However, the Maximum Read/Write Length is an I3C only feature and does not apply to Legacy I²C Transactions on the bus.