24.1.1 Data Selection
Depending on the number of bits implemented in the CLCnSELy registers, there can be as many as 256 sources available as inputs to the configurable logic. Four multiplexers are used to independently select these inputs to pass on to the next stage as indicated on the left side of the following diagram.
Data inputs in the figure are identified by a generic numbered input name.
The CLC Input Selection table correlates the generic input name to the actual signal for each CLC module. The table column labeled ‘DyS Value’ indicates the MUX selection code for the selected data input. DyS is an abbreviation for the MUX select input codes, D1S through D4S, where ‘y’ is the gate number.
| Value | Description | Value (cont.) | Description (cont.) |
|---|---|---|---|
[0] 0000 0000 | CLCIN0PPS | [32] 0010 0000 | NCO1 |
[1] 0000 0001 | CLCIN1PPS | [33] 0010 0001 | C1_OUT |
[2] 0000 0010 | CLCIN2PPS | [34] 0010 0010 | C2_OUT |
[3] 0000 0011 | CLCIN3PPS | [35] 0010 0011 | ZCD |
[4] 0000 0100 | CLCIN4PPS | [36] 0010 0100 | DSM1 |
[5] 0000 0101 | CLCIN5PPS | [37] 0010 0101 | IOC |
[6] 0000 0110 | CLCIN6PPS | [38] 0010 0110 | HLVD (not IRQ) |
[7] 0000 0111 | CLCIN7PPS | [39] 0010 0111 | CLC1 |
[8] 0000 1000 | FOSC | [40] 0010 1000 | CLC2 |
[9] 0000 1001 | HFINTOSC | [41] 0010 1001 | CLC3 |
[10] 0000 1010 | LFINTOSC | [42] 0010 1010 | CLC4 |
[11] 0000 1011 | MFINTOSC (500 kHz) | [43] 0010 1011 | CLC5 |
[12] 0000 1100 | MFINTOSC (32 kHz) | [44] 0010 1100 | CLC6 |
[13] 0000 1101 | SFINTOSC (1 MHz) | [45] 0010 1101 | CLC7 |
[14] 0000 1110 | SOSC | [46] 0010 1110 | CLC8 |
[15] 0000 1111 | EXTOSC | [47] 0010 1111 | U1TX |
[16] 0001 0000 | ADCRC | [48] 0011 0000 | U2TX |
[17] 0001 0001 | CLKR | [49] 0011 0001 | SPI1SDO |
[18] 0001 0010 | TMR0 | [50] 0011 0010 | SPI1SCK |
[19] 0001 0011 | TMR1 | [51] 0011 0011 | SPI1SS |
[20] 0001 0100 | TMR2 | [52] 0011 0100 | — |
[21] 0001 0101 | TMR3 | [53] 0011 0101 | — |
[22] 0001 0110 | TMR4 | [54] 0011 0110 | — |
[23] 0001 0111 | — | [55] 0011 0111 | I2C1SCL |
[24] 0001 1000 | CCP1 | [56] 0011 1000 | I2C1SDA |
[25] 0001 1001 | — | [57] 0011 1001 | — |
[26] 0001 1010 | PWM1S1P1_OUT | [58] 0011 1010 | — |
[27] 0001 1011 | PWM1S1P2_OUT | [59] 0011 1011 | CWG1A |
[28] 0001 1100 | PWM2S1P1_OUT | [60] 0011 1100 | CWG1B |
[29] 0001 1101 | PWM2S1P2_OUT | [61] 0011 1101 | TU16A |
[30] 0001 1110 | — | [62] 0011 1110 | TU16B |
[31] 0001 1111 | — | [63] 0011 1111 | IOCSR |
[64] 0100 0000 - [127]
0111 1111 | — | ||
