25.4.2 CLB PPS Outputs

The CLB module provides up to sixteen outputs that connect to external pins via the Peripheral Pin Select (PPS) module. For each CLB output, one row consisting of eight BLE outputs is selected through a multiplexer. The RxyPPS registers are then used to select the pin to which the output signal will be routed. Each of these outputs can be updated on the rising or falling edge of the output signal and can be synchronized or operated asynchronously to the System Clock depending on the Microchip CLB Synthesizer configuration (see Figure 25-9). These outputs can also be read via the CLBOUTH and CLBOUTL registers.

Additionally, the CLB module has the option to control the direction/tristate of the pins. The CLB module can override the settings from TRISxy register and control the direction/tristate of a pin using corresponding TRISxyPPS register (see the "PPS-Peripheral Pin Selection" section).