25.4.1 Programmable Output Edge Detectors

The CLB output edge detection is configured using the Microchip CLB Synthesizer. The Microchip CLB Synthesizer configuration determines whether the edge detectors are positive edge-triggered, negative edge-triggered, or bypassed completely. The Microchip CLB Synthesizer also determines whether the CLBOUTL and CLBOUTH registers are synchronized or operate asynchronously to the System Clock.

Figure 25-9. CLBOUTL/H Edge Detector Block Diagram
Note:
  1. These selections are configured using the Microchip CLB Synthesizer.
Figure 25-10. CLBSWOUTL/H Edge Detector Block Diagram
Note:
  1. These selections are configured using the Microchip CLB Synthesizer.
Important: The CLBSWOUTL and CLBSWOUTH registers are hardware synchronized to Q2/Q4 clocks of the System Clock.