51.4 VIH - VIL Graphs

Figure 51-30. Input Pin with LVBUF Minimum VIH vs VDD
Figure 51-31. Input Pin with LVBUF Maximum VIL vs VDD
Figure 51-32. Input Pin with Schmitt Trigger Minimum VIH vs VDD
Figure 51-33. Input Pin with Schmitt Trigger Maximum VIL vs VDD
Figure 51-34. Input Pin with Schmitt Trigger Hysteresis vs VDD
Figure 51-35. Input Pin with SMBus 2.0 Minimum VIH vs VDD
Figure 51-36. Input Pin with SMBus 2.0 Maximum VIL vs VDD
Figure 51-37. Input Pin with SMBus 3.0 Minimum VIH vs VDD
Figure 51-38. Input Pin with SMBus 3.0 Maximum VIL vs VDD
Figure 51-39. Input Pin with I2C Trigger Minimum VIH vs VDD
Figure 51-40. Input Pin with I2C Trigger Maximum VIL vs VDD
Figure 51-41. MCLR Input Pin Minimum VIH vs VDD
Figure 51-42. MCLR Input Pin Maximum VIL vs VDD