51.13 10-Bit Analog-to-Digital Converter (ADC) Graphs

Figure 51-79. ADC DNL vs ADC Code (VDD = 3.0V, TAD = 500 ns)
Figure 51-80. ADC DNL vs ADC Code (VDD = 3.0V, TAD = 1 μs)
Figure 51-81. ADC DNL vs TAD (VREF+ = VDD = 3.0V, TA = 125°C)
Figure 51-82. ADC DNL vs VREF+ (TAD = 1 μs, TA = 125°C)
Figure 51-83. ADC INL vs ADC Code (VDD = 3.0V, TAD = 500 ns)
Figure 51-84. ADC INL vs ADC Code (VDD = 3.0V, TAD = 1 μs)
Figure 51-85. ADC INL vs TAD (VREF+ = VDD = 3.0V, TA = 125°C)
Figure 51-86. ADC INL vs VREF+ (TAD = 1 μs, TA = 125°C)
Figure 51-87. ADC Gain Error vs TAD (VREF+ = VDD = 3.0V)
Figure 51-88. ADC Gain Error vs VREF+ (TAD = 1 μs)
Figure 51-89. ADC Offset Error vs TAD (VREF+ = VDD = 3.0V)
Figure 51-90. ADC Offset Error vs VREF+ (TAD = 1 μs)