6 Enhancements

The maximum number of channels that can be maintained is dependent on ISR efficiency and time slot allocated for the ISR. The ISR code efficiency will vary between compilers and will also be affected by the automatic optimization level applied at compile time. This gives great scope for experimentation to improve and optimize the ISR to increase the maximum channel limit. The sample code supplied has been written to be easy to understand rather than being the best possible solution.

ISR time slot is fixed at 256 clock cycles when using an 8-bit timer, however, making use of a 16-bit timer in CTC mode could increase the time slot. For example, having a timer reset at 512 clock cycles and doubling the crystal frequency would allow at least twice the number of channels with the same PWM base frequency.