3 Interrupt Service Routine

A logical approach for the ISR would be to increment the soft counter, determine which PWM signals should change state at that position of the PWM cycle, then implement the changes. The problem with this is that the time taken between the start of the ISR and the pin state change will vary considerably depending on the results of the PWM position tests, causing significant jitter. To eliminate this the ISR performs the pin state update immediately, then carries out the increment and position tests to prepare the state values for the start of the next interrupt cycle. On overflow of the soft counter all pin conditions are prepared for being set high and the compare values are updated with any changes made to the compbuff values. If a compare value is zero the pin condition indicator will be returned to zero, so a PWM value of zero will give an output that is permanently low. The maximum PWM pulse width will be 255/256 of the base frequency period.