4 DEBUG Operation
In order to maintain the specified jitter performance, the ISR must complete
within 256 clock cycles. The worst-case situation occurs in the softcount = 0 ISR when
all but one channels have a compare value of zero, so the DEBUG_APP option has been
included to allow checking of the ISR timing when channel quantity has been
modified.
Note: All channels being
zero is theoretically worse, but as no channel is producing a PWM pulse any timing
overflow will not be seen
Changing the DEBUG define to 1 allows the
approximate time taken by the ISR to be measured by Timer 1, with the default channel
settings changed to give the worst-case conditions, and the Timer 1 result is frequently
output on USART. Ideally the ISR time displayed should be well below 0x00FF. A debug pin
is also enabled allowing an oscilloscope to be used to view the ISR timing, with a
typical waveform shown in the figure below.
The DEBUG_APP option allows experimentation within the ISR to be monitored. The speed of the ISR is critical when trying to expand the number of channels available, so optimization or replacement of the code provided can be examined with DEBUG to determine if improvement has been made.