1.1 Pipeline Architecture and Virtual Channels

The ADC conversion block has a 12-stage pipelined architecture capable of sampling several signals in parallel. There are four input selection multiplexers with individual configurations. The separate configuration settings for the four multiplexers can be viewed as virtual channels, with one set of result registers each, all sharing the same ADC conversion block. Refer to Figure on page 1.

On the AVR XMEGA A series the multiplexer outputs can be sampled every ADC clock cycle. On the XMEGA D series a new measurement can be sampled once the previous conversion is done. Each signal propagates through the pipeline, where one bit is converted at each stage. In this way, the ADC in the XMEGA A is capable of sampling one signal every ADC clock cycle, even if each signal must propagate through all stages in the pipeline before the result is ready in the result register. The propagation time for one single signal conversion through the pipeline is seven ADC clock cycles for 12-bit conversions and five cycles for 8-bit conversions. If Gain is used the propagation time increases by one cycle. At full utilization the XMEGA A ADC delivers one result every ADC clock cycle while the XMEGA D ADC delivers one sample every 5 – 8 ADC clock cycle depending on operating mode. The relation between the XMEGA peripheral clock and the ADC clock is described in Section Conversion Speed.

The figure below shows a simplified 4-stage pipeline during conversion of two input signals. The figure shows that once the signal has been sampled into the pipeline, the first stage converts the MSB of the first signal. While the second stage is converting the next bit of the signal, the first stage now converts the MSB of the second signal.
Note: The XMEGA D3/D4 families do not have a pipelined ADC and four virtual channels per ADC.
Figure 1-1. Simplified ADC Pipeline with TWO Propagating Signals

All the four virtual channels have one MUX Control register (CHn.MUXCTRL), one Channel Control register (CHn.CTRL), and one Result register pair (CHn.RESL/CHn.RESH) each, in addition to several control bits distributed in shared registers.