1.6 Result Presentation

The ADC can be configured to present conversion results in the following formats:

  • 12 bits, right adjusted
  • 8 bits, right adjusted
  • 12 bits, left adjusted

The ADC resolution is configured using the Conversion result Resolution bit field (RESOLUTION) in Control Register B (CTRLB).

The result will be stored in the result registers for each channel. The channels have separate flags to indicate when a new conversion is ready. If the result is not read before a new conversion is done, the current result will be lost.

The DMA can be set up to transfer the result from the result register into the SRAM when a new conversion is ready. This can be done for all channels when doing sweep and store all channels in one burst.

Note: A lower resolution gives faster conversions, as there are fewer pipeline stages for the signal samples to propagate through. Therefore, selecting result presentation is a tradeoff between resolution and conversion speed.