4.3 Firmware – Digital Voltage Control

A voltage control loop is implemented to regulate the output voltage of the converter, utilizing a digital 2-pole 2-zero (2p2z) compensator. The output of this compensator directly serves as the reference value for the digital-to-analog converter (DAC) that feeds the comparator, thereby closing the feedback loop. In this architecture, the control variable is the DAC output value, which is determined by the output of the peak hold and detect circuit and the initial blanking period. The DAC control range was determined experimentally to be between 2400 and 3100; values below 2400 are blanked, as they correspond to switching frequencies above 1 MHz, while 3100 represents the maximum output of the peak hold and detect circuit. Exceeding this range may lead to instability in the control loop.

To accurately implement the digital compensator, the A and B coefficients for the 2p2z algorithm were determined using PowerSmart™.

In the design of peak current mode controlled LLC converters, a key advantage is the suppression of low-frequency voltage transient oscillations associated with the resonant behavior of the overall power stage. In this context, the term "resonance" refers not to the intrinsic resonance of the LLC tank circuit, but to the resonant frequency of the entire plant—including the output filter—which typically manifests at a much lower frequency (approximately 10 kHz in this LLC implementation). Under peak current mode control, this dominant voltage resonance is effectively mitigated as the inner current loop introduces a new dominant pole in the system’s open-loop response, typically located at roughly one-fifth the original plant resonance frequency (about 2 kHz in this LLC implementation) [3][4].

To achieve robust compensation, a single compensator pole is strategically placed at this new plant pole (2 kHz), ensuring that the control loop adequately suppresses the shifted resonance. Additionally, a high-frequency pole is introduced to compensate for the equivalent series resistance (ESR) zero of the output filter, which is a standard practice in power supply compensation design [4]. The overall loop gain is then adjusted by tuning the crossover frequency and the zero-pole pair, aligning the system’s gain and phase margins for optimal dynamic performance.

In the conceptual setup of this example, the gain relations between voltage feedback, current sense transformer feedback gain, current hold-up circuit and time delay between current peak and comparator trigger are dependent on many circuit components—inevitably to a high degree of complexity—which goes beyond the scope of this document and will be discussed in a different form later. To keep the focus of this document on the subject of basic implementation of the peripheral functions, the main loop gain was adjusted through bench experiments, starting with low gain and iterating through increasing gain levels until the crossover frequency, phase margin, and gain margin of the open loop gain met the desired stability criteria at fx >10 kHz of PHI >50° and GM <-8dB.

As the design aim was for a crossover frequency fx >10 kHz, the voltage loop is updated every 250 kHz as fx = 1/10th ~ 1/20th of the update frequency.