5 Results

Figure 5-2 presents an oscilloscope capture of various signals during converter operation. Channel 1 displays the output of the DAC, while Channel 3 shows the output of the peak hold and detect circuit. These two signals serve as inputs to the comparator, whose output also functions as the slope stop signal for the DAC slope.

The slope start signal aligns with the positive edge of PWM1H. Due to the time required for the DAC to reset, the waveform exhibits a curved shape. The DAC slope is selected to optimize performance for this configuration, with the slope enhancing the sharpness of the intersection point. When the comparator output transitions, it causes PWM1H to truncate and initiate the PWM1L cycle.

The output of the peak detect and hold circuit is reset whenever PWM1L is high. Channel 2 illustrates the rectified output of the secondary current transformer (CT). It can be observed that the secondary side switches are activated after a brief delay, ensuring that the secondary side current has increased sufficiently.

This implementation achieves a high bandwidth gain, as demonstrated below.

The frequency response of the peak current mode controlled LLC converter was evaluated under an input voltage of 39 V and an output load of 9 V at 1.6 A. As illustrated in Figure 5-2, the measured Bode plot demonstrates a significant improvement in control loop bandwidth, with the gain crossover frequency observed at 13.1 kHz. At this frequency, the phase margin is approximately 50°, indicating robust stability and excellent transient response characteristics. Furthermore, the system exhibits a gain margin of 8.7 dB, which is well above the industry-recommended minimum of 6 dB, ensuring reliable operation even in the presence of component tolerances and environmental variations. These results confirm that the implemented control strategy not only enhances the dynamic performance of the LLC converter but also provides a stable and resilient solution suitable for demanding power supply applications.

During pulsed load step testing of the peak current mode controlled LLC converter, the output voltage (Channel 4, AC coupled) and rectified output current (Channel 2) were monitored to assess transient response at a 0%-100%-0% load pulse applied every 5 ms. As depicted in the oscilloscope capture Figure 5-3, the output voltage demonstrates minimal deviation and rapid settling following each load transition. This swift voltage recovery is a direct consequence of the high control loop bandwidth, as established in the Bode plot analysis, which enables the feedback system to promptly counteract load disturbances. The observed performance underscores the effectiveness of the implemented control strategy in achieving both robust dynamic regulation and stable operation under demanding, fast-changing load conditions that are critical for modern power supply applications.

A critical aspect of the LLC converter design is the careful selection of the burden resistor and the differential amplifier gain within the peak hold and detection circuit, as these parameters directly influence the shape and fidelity of the feedback signal waveform. Accurate feedback is essential for precise current mode control, and any deviation in these component values can introduce errors or distortions that compromise system performance. Furthermore, the RC network in the peak hold and detect circuit must be meticulously configured so that its time constant is well-matched to the minimum PWM1H on-time. This alignment ensures that the peak detection accurately tracks the fastest switching events without introducing lag or excessive filtering, which is particularly important at high operating frequencies.

The original ILLC board is characterized by a relatively flat tank response and operates at a very high switching frequency, conditions that can push the digital-to-analog converter (DAC) to its operational limits and potentially constrain overall system performance. By optimizing the design to operate within the 200–400 kHz frequency range, the converter is expected to achieve improved efficiency and reliability. In this range, the control and detection circuits can function within their optimal bandwidth, enabling more accurate peak detection and robust feedback, which together contribute to enhanced dynamic response and system stability.