1.1 Basic Bus Signals

The master initiates every communication on the bus down to the bit-level. This means that for every bit that is to be transmitted, regardless of direction, the master has to initiate the bit transmission. This is always done by pulling the bus low, which will synchronize the timing logic of all units. There are five basic commands for communication on the 1-Wire bus: “Write 1”, “Write 0”, “Read”, “Reset”, and “Presence”.

“Write 1” signal

A “Write 1” signal is shown in the figure below. The master pulls the bus low for 1 to 15 μs. It then releases the bus for the rest of the time slot.

Figure 1-1. "Write 1" Signal

“Write 0” signal

A “Write 0” signal is shown in the figure below. The master pulls the bus low for a period of at least 60 μs, with a maximum length of 120 μs.

Figure 1-2. "Write 0" Signal

“Read” signal

A “Read” signal is shown in the figure below. The master pulls the bus low for 1 to 15 μs. The slave then holds the bus low if it wants to send a ‘0’. If it wants to send a ‘1’, it simply releases the line. The bus should be sampled 15 μs after the bus was pulled low. As seen from the master’s side, the “Read” signal is, in essence, a “Write 1” signal. It is the internal state of the slave, rather than the signal itself that dictates whether it is a “Write 1” or “Read” signal.

Figure 1-3. “Read” Signal

“Reset/Presence” signal

A “Reset” and “Presence” signal is shown in the figure below. Note that the time scale is different from the first waveforms. The master pulls the bus low for at least eight time slots, or 480 μs, and then releases it. This long low period is called the “Reset” signal. If there is a slave present, it should then pull the bus low within 60 μs after it was released by the master and hold it low for at least 60 μs. This response is called a “Presence” signal. If no presence signal is issued on the bus, the master must assume that no device is present on the bus, and further communication is not possible.

Figure 1-4. "Reset" and "Presence" Signal

Generating the signals in software

Generating the 1-Wire signals on an AVR in software only is straightforward. Simply changing the direction and value of a general purpose I/O pin and generating the required delay is sufficient. A detailed description is given in the Implementation section.

Generating the signals with a UART

The basic 1-Wire signals can also be generated by a UART. This requires both the TXD and RXD pins to be connected to the bus. An external open-collector or open-drain buffer is required to allow slave devices to pull the bus low when the UART output is high. The figure below shows the connection using NPN-transistors. The resistor values are suggested values only. See the data sheet of the slave device for more information on the recommended pull-up resistance.

Figure 1-5. Open Collector Buffer

The UART data format used when generating 1-Wire signals is eight data bits, no parity, and one stop byte. One UART data frame is used to generate the waveform for one bit or one RESET/PRESENCE sequence. The table below shows how to set up the UART module to generate the waveforms and how to interpret the received data. The corresponding UART bit patterns are shown in Figure 1-6, Figure 1-7, Figure 1-8, Figure 1-9, and Figure 1-10.

Table 1-1. UART Signaling
SignalBaud RateTransmit ValueReceive Value
Write 1115200FFhFFh
Write 011520000h00h
Read115200FFhFFh equals a ‘1’ bit. Anything else equals a ‘0’ bit.
Reset/Presence9600F0hF0h equals no presence. Anything else equals presence.
Figure 1-6. "Write 1" Signal and UART Bit Pattern
Figure 1-7. "Write 0" Signal and UART Bit Pattern
Figure 1-8. "Read 0" Signal and UART Bit Pattern
Figure 1-9. "Read 1" Signal and UART Bit Pattern
Figure 1-10. Reset/Presence Signal with the UART