37.4 Supply Voltage

Table 37-4. Supply Voltage
SymbolMin.Typ. ✝Max.UnitConditions
Supply Voltage(1)
VDD1.85.5V
Slew Rate——0.25V/μs1.8V ≤ VDD ≤ 5.5V
RAM Data Retention(2)
VDR1.7——VDevice in Power-Down mode
Power-on Reset Release Voltage(4)
VPOR—1.6—VBOD disabled(3)
tPOR—1—μsBOD disabled(3)
Power-on Reset Re-Arm Voltage(4)
VPORR—1.25—VBOD disabled(3)
tPORR—2.7—μsBOD disabled(3)
VDD Rise Rate to Ensure Internal Power-on Reset Signal(4)
SVDD0.05——V/msBOD disabled(3)

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

Note:
  1. During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. If the supply voltage VDD is below VBOD for BODLEVEL0, the erase attempt will fail.
  2. This is the limit to which VDD can be lowered in sleep mode without losing RAM data.
  3. Refer to RST and BOD for BOD trip point information.
  4. Refer to Figure 37-1.
Figure 37-1. POR and POR Re-Arm with Slow Rising VDD
Note: When POR is low, the device is held in Reset.