37.14 SPI - Timing Characteristics
Symbol | Description | Min. | Typ.✝ | Max. | Unit | Condition |
---|---|---|---|---|---|---|
fSCK * | SCK clock frequency | — | — | fCLK_PER/2 | MHz | |
TSCK * | SCK period | 2 × TCLK_PER | — | — | ns | |
tSCKW | SCK high/low width | — | 0.5 × TSCK | — | ns | |
tMIS | MISO setup to SCK | — | TCLK_PER | — | ns | |
tMIH | MISO hold after SCK | — | 0 | — | ns | |
tMOS | MOSI setup to SCK | — | 0.5 × TSCK | — | ns | |
tMOH | MOSI hold after SCK | — | 0.5 × TSCK | — | ns | |
✝ Unless otherwise specified, data in the “Typ.” column is at TA = 25°C and VDD = 3.0V. These parameters are not tested and are for design guidance only. * These parameters are characterized but not tested in production. |
Symbol | Description | Min. | Typ.✝ | Max. | Unit | Condition |
---|---|---|---|---|---|---|
fSSCK * | Client SCK clock frequency | — | — | fCLK_PER/6 | MHz | |
TSSCK * | Client SCK period | 6 × TCLK_PER | — | — | ns | |
tSSCKW * | SCK high/low width | 3 × TCLK_PER | — | — | ns | |
tSIS * | MOSI setup to SCK | 0 | — | — | ns | |
tSIH * | MOSI hold after SCK | 3 × TCLK_PER | — | — | ns | |
tSSS * | SS setup to SCK | TCLK_PER | — | — | ns | |
tSSH * | SS hold after SCK | TCLK_PER | — | — | ns | |
tSDLY | Interbyte delay |
5 - fCLK_PER/(2 × fSCK) | — | — | ns | fSSCK < fCLK_PER/10 |
0 | fSSCK ≥ fCLK_PER/10 | |||||
tSOS | MISO valid after SCK | — | tSR | — | ns | |
— | ||||||
tSOSS | MISO setup after SS low | — | tSR | — | ns | |
tSOSH | MISO hold after SS low | — | tSR | — | ns | |
✝ Unless otherwise specified, data in the “Typ.” column is at TA = 25°C and VDD = 3.0V. These parameters are not tested and are for design guidance only. * These parameters are characterized but not tested in production. |