37.15 TWI

Figure 37-7. TWI - Timing Requirements

Table 37-21. TWI - Timing Specifications
Symbol	Description	Min.	Typ.✝	Max.	Unit	Condition
V_DD	Supply voltage range	1.8	—	5.5	V	f_SCL ≤ 400 kHz
V_DD	Supply voltage range	2.2 *	—	5.5 *	V	f_SCL ≤ 1 MHz
f_SCL *	SCL clock frequency	—	—	1000	kHz	Max. frequency requires system clock at 10 MHz
V_HYS *	Hysteresis of Schmitt Trigger inputs	0.05×V_DD		0.4×V_DD	V
V_OL	Output low voltage	—	—	0.4	V	I_load = 5 mA, V_DD > 2V
V_OL	Output low voltage	—	—	0.2×V_DD	V	I_load = 3 mA, V_DD ≤ 2V
I_OL *	Low-level output current	5	—	—	mA	V_OL = 0.4V
I_OL *	Low-level output current	10	—	—	mA	V_OL = 0.4V V_DD ≥ 2.7V
C_B *	Capacitive load for each bus line	—	—	400	pF	f_SCL ≤ 100 kHz
		—	—	400		f_SCL ≤ 400 kHz
		—	—	550		f_SCL ≤ 1 MHz V_DD > 2.75V
t_R *	Rise time for both SDA and SCL	—	—	1000	ns	f_SCL ≤ 100 kHz
		20	—	300		f_SCL ≤ 400 kHz
		—	—	120		f_SCL ≤ 1 MHz
t_OF *	Output fall time from V_IHmin to V_ILmax	—	—	250	ns	f_SCL ≤ 100 kHz 10 pF < C_B < 400 pF
		20×(V_DD/5.5V)	—	250		f_SCL ≤ 400 kHz 10 pF < C_B < 400 pF
		20×(V_DD/5.5V)	—	120		f_SCL ≤ 1 MHz 10 pF < C_B < 400 pF
t_SP *	Spikes suppressed by the input filter	0	—	50	ns
I_L *	Input current for each I/O pin	—	—	1	µA	0.1×V_DD < V_I < 0.9×V_DD
C_I *	Capacitance for each I/O pin	—	—	10	pF
R_P *	Value of pull-up resistor	(V_DD-V_OL(max)) /I_OL	—	1000 ns/(0.8473×C_B)	Ω	f_SCL ≤ 100 kHz
		(V_DD-V_OL(max)) /I_OL	—	300 ns/(0.8473×C_B)		f_SCL ≤ 400 kHz
		(V_DD-V_OL(max)) /I_OL	—	120 ns/(0.8473×C_B)		f_SCL ≤ 1 MHz
t_{HD_STA} *	Hold time (repeated) Start condition	4.0	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.26	—	—		f_SCL ≤ 1 MHz
T_LOW *	Low period of SCL Clock	4.7	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.35	—	—		f_SCL ≤ 1 MHz
T_HIGH *	High period of SCL Clock	4.0	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.26	—	—		f_SCL ≤ 1 MHz
t_{SU_STA} *	Setup time for a repeated Start condition	4.7	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.26	—	—		f_SCL ≤ 1 MHz
t_{HD_DAT} *	Data hold time across all corners	—	0	—	ns	SDAHOLD[1:0] = `0x0`
t_{HD_DAT} *	Data hold time across all corners	300	—	900	ns	SDAHOLD[1:0] = `0x3`
t_{SU_DAT} *	Data setup time	250	—	—	ns	f_SCL ≤ 100 kHz
		100	—	—		f_SCL ≤ 400 kHz
		50	—	—		f_SCL ≤ 1 MHz
t_{SU_STO} *	Setup time for Stop condition	4	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.26	—	—		f_SCL ≤ 1 MHz
t_BUF *	Bus free time between a Stop and Start condition	4.7	—	—	µs	f_SCL ≤ 100 kHz
t_BUF *	Bus free time between a Stop and Start condition	1.3	—	—	µs	f_SCL ≤ 400 kHz
t_CS *	Client Clock Stretching delay	—	—	250	ns
✝ Data found in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. * These parameters are characterized but not tested in production.

AVR32DA28/32/48

37.15 TWI