7.9.2.4 System Configuration 0
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the Reset value.
| Name: | SYSCFG0 |
| Offset: | 0x05 |
| Reset: | 0xC0 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCSRC[1:0] | CRCSEL | RSTPINCFG[1:0] | EESAVE | ||||||
| Access | R | R | R | R | R | R | |||
| Reset | 1 | 1 | 0 | 0 | 0 | 0 | |||
Bits 7:6 – CRCSRC[1:0] CRC Source
| Value | Name | Description |
|---|---|---|
| 0x0 | FLASH | CRC of full Flash (boot, application code, and application data) |
| 0x1 | BOOT | CRC of the Boot section |
| 0x2 | BOOTAPP | CRC of the Application code and Boot sections |
| 0x3 | NOCRC | No CRC |
Bit 5 – CRCSEL CRC Mode Selection
| Value | Name | Description |
|---|---|---|
| 0x0 | CRC16 | CRC-16-CCITT |
| 0x1 | CRC32 | CRC-32 (IEEE 802.3) |
Bits 3:2 – RSTPINCFG[1:0] Reset Pin Configuration
| Value | Name | Description |
|---|---|---|
| 0x0 | INPUT | PF6 configured as general input pin. |
| 0x1 | - | Reserved |
| 0x2 | RESET | External Reset enabled on PF6 |
| 0x3 | - | Reserved |
Bit 0 – EESAVE EEPROM Save During Chip Erase
| Value | Description |
|---|---|
| 0 | EEPROM erased during Chip Erase |
| 1 | EEPROM not erased under Chip Erase, regardless of whether the device is locked or not |