4 Signal Description

The following table provides details on signal names classified by peripherals.

Table 4-1. Signal Description List
Signal Name	Function	Type	Active Level	Voltage Reference	Comments
Power Supplies
VDDIO	Peripherals I/O Lines Power Supply	Power	–	–	–
VDDIN	Voltage Regulator Input, AFE, DAC, and Analog Comparator Power Supply⁽¹⁾	Power	–	–	–
VDDOUT	Voltage Regulator Output	Power	–	–	–
VDDPLL	PLLA Power Supply	Power	–	–	–
VDDPLLUSB	USB PLL and Oscillator Power Supply	Power	–	–	–
VDDCORE	Powers the core, the embedded memories and the peripherals	Power	–	–	–
GND, GNDPLL, GNDPLLUSB, GNDANA, GNDUTMI	Ground	Ground	–	–	–
VDDUTMII	USB Transceiver Power Supply	Power	–	–	–
VDDUTMIC	USB Core Power Supply	Power	–	–	–
GNDUTMI	USB Ground	Ground	–	–	–
Clocks, Oscillators, and PLLs
XIN	Main Oscillator Input	Input	–	VDDIO	If any signal is not used, its PIO pin should be setup as an output, driven low, and attached to a dedicated trace on the board in order to reduce current consumption.
XOUT	Main Oscillator Output	Output	–
XIN32	Slow Clock Oscillator Input	Input	–
XOUT32	Slow Clock Oscillator Output	Output	–
PCK0–PCK2	Programmable Clock Output	Output	–		–
Real Time Clock
RTCOUT0	Programmable RTC Waveform Output	Output	–	VDDIO	–
RTCOUT1	Programmable RTC Waveform Output	Output	–	VDDIO	–
Serial Wire Debug/JTAG Boundary Scan
SWCLK/TCK	Serial Wire Clock/Test Clock (Boundary scan mode only)	Input	–	VDDIO	–
TDI	Test Data In (Boundary scan mode only)	Input	–		–
TDO/TRACESWO	Test Data Out (Boundary scan mode only)	Output	–		–
SWDIO/TMS	Serial Wire Input/Output /Test Mode Select (Boundary scan mode only)	I/O / Input	–		–
JTAGSEL	JTAG Selection	Input	High		–
Trace Debug Port
TRACECLK	Trace Clock	Output	–	VDDIO	PCK3 is used for ETM
TRACED0–TRACED3	Trace Data	Output	–	VDDIO	–
Flash Memory
ERASE	Flash and NVM Configuration Bits Erase Command	Input	High	VDDIO	–
Reset/Test
NRST	Synchronous Microcontroller Reset	I/O	Low	VDDIO	–
TST	Test Select	Input	–	VDDIO	–
Universal Asynchronous Receiver Transceiver - UART(x=[0:4])
URXDx	UART Receive Data	Input	–	–	PCK4 can be used to generate the baud rate
UTXDx	UART Transmit Data	Output	–	–	PCK4 can be used to generate the baud rate
PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE
PA0–PA31	Parallel I/O Controller A	I/O	–	VDDIO	–
PB0–PB9, PB12–PB13	Parallel I/O Controller B	I/O	–		–
PC0– PC31	Parallel I/O Controller C	I/O	–		–
PD0–PD31	Parallel I/O Controller D	I/O	–	–	–
PE0–PE5	Parallel I/O Controller E	I/O	–	–	–
PIO Controller - Parallel Capture Mode
PIODC0–PIODC7	Parallel Capture Mode Data	Input	–	VDDIO	–
PIODCCLK	Parallel Capture Mode Clock	Input	–		–
PIODCEN1–PIODCEN2	Parallel Capture Mode Enable	Input	–		–
External Bus Interface
D[15:0]	Data Bus	I/O	–	–	–
A[23:0]	Address Bus	Output	–	–	–
NWAIT	External Wait Signal	Input	Low	–	–
Static Memory Controller (SMC)
NCS0–NCS3	Chip Select Lines	Output	Low	–	–
NRD	Read Signal	Output	Low	–	–
NWE	Write Enable	Output	Low	–	–
NWR0–NWR1	Write Signal	Output	Low	–	–
NBS0–NBS1	Byte Mask Signal	Output	Low	–	–
NAND Flash Logic
NANDOE	NAND Flash Output Enable	Output	Low	–	–
NANDWE	NAND Flash Write Enable	Output	Low	–	–
High-Speed Multimedia Card Interface (HSMCI)
MCCK	Multimedia Card Clock	O	–	–	–
MCCDA	Multimedia Card Slot A Command	I/O	–	–	–
MCDA0–MCDA3	Multimedia Card Slot A Data	I/O	–	–	–
Universal Synchronous Asynchronous Receiver Transmitter (USART(x=[0:2]))
SCKx	USARTx Serial Clock	I/O	–	–	PCK4 can be used to generate the baud rate
TXDx	USARTx Transmit Data	I/O	–	–
RXDx	USARTx Receive Data	Input	–	–
RTSx	USARTx Request To Send	Output	–	–
CTSx	USARTx Clear To Send	Input	–	–
DTRx	USARTx Data Terminal Ready	Output	–	–
DSRx	USARTx Data Set Ready	Input	–	–
DCDx	USARTx Data Carrier Detect	Input	–	–
RIx	USARTx Ring Indicator	Input	–	–
LONCOL1	LON Collision Detection	Input	–	–
Synchronous Serial Controller (SSC)
TD	SSC Transmit Data	Output	–	–	–
RD	SSC Receive Data	Input	–	–	–
TK	SSC Transmit Clock	I/O	–	–	–
RK	SSC Receive Clock	I/O	–	–	–
TF	SSC Transmit Frame Sync	I/O	–	–	–
RF	SSC Receive Frame Sync	I/O	–	–	–
Inter-IC Sound Controller (I2SC[1..0])
I2SCx_MCK	Host Clock	Output	–	VDDIO	GCLK[PID] can be used to generate the baud rate
I2SCx_CK	Serial Clock	I/O	–	VDDIO
I2SCx_WS	I²S Word Select	I/O	–	VDDIO
I2SCx_DI	Serial Data Input	Input	–	VDDIO
I2SCx_DO	Serial Data Output	Output	–	VDDIO
Image Sensor Interface (ISI)
ISI_D0–ISI_D11	Image Sensor Data	Input	–	–	–
ISI_MCK	Image sensor Reference clock. No dedicated signal, PCK1 can be used.	Output	–	–	–
ISI_HSYNC	Image Sensor Horizontal Synchro	Input	–	–	–
ISI_VSYNC	Image Sensor Vertical Synchro	Input	–	–	–
ISI_PCK	Image Sensor Data clock	Input	–	–	–
Timer Counter (TC(x=[0:11]))
TCLKx	TC Channel x External Clock Input	Input	–	–	PCK6 can be used as an input clock PCK7 can be used as an input clock for TC0.Ch0 only
TIOAx	TC Channel x I/O Line A	I/O	–	–
TIOBx	TC Channel x I/O Line B	I/O	–	–
Pulse-Width Modulation Controller (PWMC(x=[0..1]))
PWMCx_PWMH0– PWMCx_PWMH3	Waveform Output High for Channel 0–3	Output	–	–	–
PWMCx_PWML0– PWMCx_PWML3	Waveform Output Low for Channel 0–3	Output	–	–	Only output in complementary mode when dead time insertion is enabled.
PWMCx_PWMFI0–PWMCx_PWMFI2	Fault Input	Input	–	–	–
PWMCx_PWMEXTRG0–PWMCx_PWMEXTRG1	External Trigger Input	Input	–	–	–
Serial Peripheral Interface (SPI(x=[0..1]))
SPIx_MISO	Host In Client Out	I/O	–	–	–
SPIx_MOSI	Host Out Client In	I/O	–	–	–
SPIx_SPCK	SPI Serial Clock	I/O	–	–	–
SPIx_NPCS0	SPI Peripheral Chip Select 0	I/O	Low	–	–
SPIx_NPCS1–SPIx_NPCS3	SPI Peripheral Chip Select	Output	Low	–	–
Quad I/O SPI (QSPI)
QSCK	QSPI Serial Clock	Output	–	–	–
QCS	QSPI Chip Select	Output	–	–	–
QIO0–QIO3	QSPI I/O QIO0 is QMOSI Host Out Client In QIO1 is QMISO Host In Client Out	I/O	–	–	–
Two-Wire Interface (TWIHS (x=0..2))
TWDx	TWIx Two-wire Serial Data	I/O	–	–	–
TWCKx	TWIx Two-wire Serial Clock	I/O	–	–	–
Analog
VREFP	ADC, DAC and Analog Comparator Positive Reference	Analog	–	–	–
VREFN	ADC, DAC and Analog Comparator Negative Reference Must be connected to GND or GNDANA.	Analog	–	–	–
12-bit Analog Front End - (x=[0..1])
AFEx_AD0–AFEx_AD11 ⁽²⁾	Analog Inputs	Analog, Digital	–	–	–
AFEx_ADTRG	ADC Trigger	Input	–	VDDIO	–
12-bit Digital-to-Analog Converter (DAC)
DAC0–DAC1	Analog Output	Analog, Digital	–	–	–
DATRG	DAC Trigger	Input	–	VDDIO	–
Fast Flash Programming Interface (FFPI)
PGMEN0–PGMEN1	Programming Enabling	Input	–	VDDIO	–
PGMM0–PGMM3	Programming Mode	Input	–	VDDIO	–
PGMD0–PGMD15	Programming Data	I/O	–		–
PGMRDY	Programming Ready	Output	High		–
PGMNVALID	Data Direction	Output	Low		–
PGMNOE	Programming Read	Input	Low		–
PGMNCMD	Programming Command	Input	Low		–
USB High Speed (USBHS)
HSDM	USB High -Speed Data -	Analog, Digital	–	VDDUTMII	–
HSDP	USB High-Speed Data +	Analog, Digital	–	VDDUTMII	–
VBG	Bias Voltage Reference for USB	Analog	–	–	–
Ethernet MAC 10/100 - GMAC
GREFCK	Reference Clock	Input	–	–	RMII only
GTXCK	Transmit Clock	Input	–	–	MII only
GRXCK	Receive Clock	Input	–	–	MII only
GTXEN	Transmit Enable	Output	–	–	–
GTX0 - GTX3	Transmit Data	Output	–	–	GTX0–GTX1 only in RMII
GTXER	Transmit Coding Error	Output	–	–	MII only
GRXDV	Receive Data Valid	Input	–	–	MII only
GRX0 - GRX3	Receive Data	Input	–	–	GRX0–GRX1 only in RMII
GRXER	Receive Error	Input	–	–	–
GCRS	Carrier Sense	Input	–	–	MII only
GCOL	Collision Detected	Input	–	–	MII only
GMDC	Management Data Clock	Output	–	–	–
GMDIO	Management Data Input/Output	I/O	–	–	–
GTSUCOMP	TSU timer comparison valid	Output	–	–	Active Low
Controller Area Network - MCAN (x=[0:1])
CANRXx	CAN Receive	Input	–	–	CANRX1 is available on PD28 for 100-pin only CANRX1 is available on PC12 for 144-pin only
CANTXx	CAN Transmit	Output	–	–	PCK5 can be used for CAN clock PCK6 and PCK7 can be used for CAN timestamping
MediaLB - (MLB)
MLBCLK	MLB Clock	input	–	–	–
MLBSIG	MLB Signal	I/O	–	–	–
MLBDAT	MLB Data	I/O	–	–	–

Note:

Refer to the Active Mode section in the Power Considerations chapter for restrictions on the voltage range of analog cells.
AFE0_AD11 is not an actual pin but is connected to a temperature sensor.