2.3 Assumed Safety Goals
The safety requirements of these devices focus on the generation of stable, accurate and reliable clock signals for other functional blocks in the modules and end system. These devices include internal monitoring functions that can be accessed through the SPI or I2C interface, output on the GPIO pin, or output on the GPO pins of the ZLA30831, ZLA30851 and ZLA30931. The functions include:
- Checking the synthesizer APLL is locked to the oscillator on the OSCI pin
- Reading the status of input reference monitors
- Checking for a valid input reference for the DPLL
- Reading the state of the DPLL
- Reading the frequency offset and phase offset of the DPLL vs. its selected reference
- Reading the frequency offset and phase offset of other references vs. the DPLL
- Reading the boot status of the device including which of two internal firmware versions the device is running
The table below defines the correct function for these devices:
| Target | To provide multiple reliable clock signals for an end system. Such systems may perform, as examples, automotive intelligent cockpit or autonomous driving, networking, communication (wired or wireless), sensing, and audio/video generation/ reception. |
| Description |
The correct clock signal generation occurs when the system controller powers up and sends appropriate control signals to the device. The device may have been correctly preconfigured in One-Time-Programmable (OTP) memory or flash memory, depending on part number, for the chosen clock parameters including frequency, signal format, duty cycle, and phase. The clock output signals must meet all datasheet specifications (including, for example, published phase noise performance). The following failure modes are considered:
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