2.1 Intended Use the Devices

These devices generate up to eight CMOS output clocks signals or up to four differential output clocks signals. Most of the devices perform jitter attenuation, and several have increasingly sophisticated system timing behaviors as described in the next section. Communication with the devices occurs over 3-wire SPI or I²C bus or GPIO pin, allowing functionality to be tested and changed. There are several functional safety internal monitoring functions accessible through the bus and the GPIO, listed in the Assumed Safety Goals section and described in detail in the Safety Mechanisms section.

The products are intended to supply high performance clock signals to subsystem designs that require, for example, 100 MHz for PCIe and 156.25 MHz for Ethernet.

Customized clock configurations are created by the customer using the Sequoia Graphical User Interface (GUI) provided by Microchip.