Introduction

PolarFire® SoC FPGA devices integrate a fifth-generation flash-based FPGA fabric architecture that includes embedded Math blocks optimized specifically for Digital Signal Processing (DSP) applications such as Finite Impulse Response (FIR) filters, Infinite Impulse Response (IIR) filters, and Fast Fourier Transform (FFT) functions.

This document describes the DSP FIR filter demo design and how to run the demo on a PolarFire SoC Discovery Kit. The DSP FIR filter demo is implemented using Libero® SoC. The demo design consists of:

• A 127 tap FIR filter with re-loadable coefficients.
• A 256 point FFT on filter output to view spectrum.
• An UART interface to the host PC to load the filter coefficients and input signals (low-pass, high-pass, band-pass, and band-stop frequencies).
• A Host PC GUI application to generate and interface with the demo design running on the PolarFire SoC FPGA device. The GUI also plots the input/output waveforms and the required spectrum.