2 Demo Design Description

The DSP FIR Filter design is developed to showcase the Math block capabilities of PolarFire SoC for implementing filtering applications.

In the design, the host interface and the FIR filter are implemented in the fabric for low-pass, high-pass, band-pass, and band-stop filtering operations. The testbench provided for this demo uses pre-generated filter coefficients and input signals (low-pass, high-pass, band-pass, and band-stop frequencies) and passes the values to the demo design. The CoreFIR_PF IP suppresses unwanted frequency components, and the CoreFFT IP generates the output spectrum to verify the filtering operation.

The following figure shows the top-level block diagram of the DSP FIR filter design.

Figure 2-1. Block Diagram

The following steps describe the data flow in the design:

  1. Upon UART handshaking (sending and receiving the known patterns over the UART bus to pre-verify the serial channel before actual usage), the GUI application running on the host PC sends the filter coefficients followed by filter input data.
  2. UART IF block creates 16-bit packets and stores the data in the corresponding input data buffers (FFT Imaginary Buffer, FFT Real Buffer, FIR IN buffer, and FIR OUT Buffer) and coefficient buffers (Coef Buffer).

  3. Filter Control FSM controls the following operations:

    • Reading the data from buffers
    • Writing the data into CoreFIR IP
  4. Once the CoreFIR generates the output response, the data is stored in the FIR OUT buffer.
  5. The CoreFIR output is sent to CoreFFT. After receiving, the CoreFFT generates the frequency spectrum of the filtered data and generates the real and imaginary output data. The CoreFFT-generated real and imaginary outputs are stored in FFT Real and FFT Imaginary buffers.
  6. UART IF block reads the data from FIR and FFT output buffers and sends the data to GUI through UART. The GUI plots the received data.