18 Introduction

The Three-phase Pulse Width Modulation (PWM) generates carrier-based, center-aligned PWM to trigger the switches of a three-phase inverter. The module also introduces a configurable dead time to avoid dead short circuits. A delay time can be introduced to synchronize multiple three-phase PWM block instantiations for multi-axis or for harmonic cancellation in the case of multi-level inverters.

Summary

The following table provides a summary of the Three-phase PWM IP characteristics.

Core VersionThis document applies to Three-phase PWM v4.2.
Supported Device Families
  • PolarFire® SoC
  • PolarFire
  • RTG4™
  • IGLOO® 2
  • SmartFusion® 2
Supported Tool FlowRequires Libero® SoC v11.8 or later releases.
LicensingComplete encrypted RTL code is provided for the core, enabling the core to be instantiated with SmartDesign. Simulation, Synthesis, and Layout can be performed with Libero software. Three-phase PWM is licensed with encrypted RTL that must be purchased separately. For more information, see Three-phase PWM.

Features

Three-phase PWM has the following key features:

  • Generate three-phase pulse-width modulated signals based on three independent references
  • Introduce a delay time to adjust the phase of PWM cycles between two three-phase PWM blocks
  • Introduce a configurable dead time to avoid dead shorts in the inverter bridge
  • Enable or disable signal to shut down the PWM output signals within one system clock cycle
  • Generate timing pulses for other blocks, configurable as one or two pulses per period

Implementation of IP Core in Libero Design Suite

IP core must be installed to the IP Catalog of the Libero® SoC software. This is done automatically through the IP Catalog update function in the Libero SoC software, or the IP core can be manually downloaded from the catalog. Once the IP core is installed in the Libero SoC software IP Catalog, the core can be configured, generated, and instantiated within the SmartDesign tool for inclusion in the Libero project list.