7 Introduction
(Ask a Question)The T-Format interface IP has been designed to provide an interface for the FPGAs to communicate with various compliant Tamagawa products such as rotary encoders.
Summary
(Ask a Question)The following table provides a summary of the T-Format interface characteristics.
| Core Version | This document applies to T-Format Interface v1.1. |
| Supported Device Families |
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| Supported Tool Flow | Requires Libero® SoC v11.8 or later releases. |
| Licensing | Complete encrypted RTL code is provided for the core, enabling the core to be instantiated with SmartDesign. Simulation, Synthesis, and Layout are performed with Libero software. T-Format Interface is licensed with encrypted RTL that must be purchased separately. For more information, see T-Format Interface. |
Features
(Ask a Question)T-Format Interface has the following key features:
- Transmits and receives serial data from the physical layer (RS-485 interface)
- Aligns data as per T-Format and provides this data as registers that are read by subsequent blocks
- Checks for errors, such as parity, Cyclic Redundancy Check (CRC) mismatch, transmit errors, and so on, are reported by the external device
- Provides an alarm function that is triggered if the number of fault occurrences exceeds a configured threshold
- Provides ports for an external CRC generator block so that the user modifies the CRC polynomial if necessary
Implementation of IP Core in Libero Design Suite
(Ask a Question)IP core must be installed to the IP Catalog of the Libero SoC software. This is done automatically through the IP Catalog update function in the Libero SoC software, or the IP core is manually downloaded from the catalog. Once the IP core is installed in the Libero SoC software IP Catalog, the core is configured, generated, and instantiated within the SmartDesign tool for inclusion in the Libero project list.
