10.6.2 Standard Communication

The main interface to the target processor is via standard communication. It contains the connections to the high voltage (V_PP), V_DD sense lines, as well as clock and data connections required for programming and connecting with the target devices.

The V_PP high-voltage lines can produce a variable voltage that can swing from 0-14V to satisfy the voltage requirements of the specific emulation processor.

The V_DD sense connection draws very little current from the target processor. The actual power comes from the MPLAB ICD 5 In-Circuit Debugger system, as the V_DD sense line is used as a reference only to track the target voltage. The V_DD connection is isolated with an optical switch.

The clock and data connections are interfaces with the following characteristics:

• Clock and data signals are in high-impedance mode (even when no power is applied to the MPLAB ICD 5 In-Circuit Debugger system).
• Clock and data signals are protected from high voltages caused by faulty target systems, or improper connections.
• Clock and data signals are protected from high current caused from electrical shorts in faulty target systems.