44.4.4 Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications

Figure 44-7. Reset, Watchdog Timer, and Power-up Timer Timing
Note:
  1. Asserted low.
Figure 44-8. Brown-out Reset Timing and Characteristics
Note:
  1. Only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0.
Table 44-10. 
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
RST01*TMCLRMCLR Pulse-Width Low to ensure Reset———μs
RST02*TIOZI/O high-impedance from Reset detection——2μs
RST03TWDTWatchdog Timer Time-out Period—16—msWDTCPS = 00100
RST04*TPWRTPower-up Timer Period—65—ms
RST05TOSTOscillator Start-up Timer Period(1,2)—1024—TOSC
RST06VBORBrown-out Reset Voltage

—

—

2.65

1.9

—

—

V

V

BORV = 0

BORV = 1

RST07VBORHYSBrown-out Reset Hysteresis—60—mVBORV = 0
RST08TBORDCBrown-out Reset Response Time—3—μs
RST09VLPBORLow-Power Brown-out Reset Voltage1.81.92.2V

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
  2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.