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PIC16F17114/15/24/25/44/45 Full-Featured 8/14/20-Pin Microcontrollers

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9 Memory Organization
9.7 Register Definitions: Memory Organization
9.7.8 WREG
WREG

Introduction
PIC16F171 Family Summary
Core Features
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC16F171 Microcontrollers
5 Register and Bit Naming Conventions
6 Register Legend
7 Enhanced Mid-Range CPU
8 Device Configuration
9 Memory Organization
- 9.1 Program Memory Organization
- 9.2 Data Memory Organization
- 9.3 STATUS Register
- 9.4 PCL and PCLATH
- 9.5 Stack
- 9.6 Indirect Addressing
- 9.7 Register Definitions: Memory Organization
  - 9.7.1 INDF0
    INDF0
  - 9.7.2 INDF1
    INDF1
  - 9.7.3 PCL
    PCL
  - 9.7.4 STATUS
    STATUS
  - 9.7.5 FSR0
    FSR0
  - 9.7.6 FSR1
    FSR1
  - 9.7.7 BSR
    BSR
  - 9.7.8 WREG
    WREG
  - 9.7.9 PCLATH
    PCLATH
- 9.8 Register Summary - Memory Organization
10 Resets
11 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
12 INT - Interrupts
13 Power-Saving Modes
14 WWDT - Windowed Watchdog Timer
15 NVM - Nonvolatile Memory Control
16 I/O Ports
17 IOC - Interrupt-on-Change
18 PPS - Peripheral Pin Select Module
19 CRC - Cyclic Redundancy Check Module with Memory Scanner
20 PMD - Peripheral Module Disable
21 CLKREF - Reference Clock Output Module
22 TMR0 - Timer0 Module
23 TMR1 - Timer1 Module with Gate Control
24 TMR2 - Timer2 Module
25 NCO - Numerically Controlled Oscillator Module
26 CWG - Complementary Waveform Generator Module
27 CCP - Capture/Compare/PWM Module
28 Capture, Compare, and PWM Timers Selection
29 PWM - Pulse-Width Modulator with Compare
30 CLC - Configurable Logic Cell
31 MSSP - Host Synchronous Serial Port Module
32 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
33 ADC - Analog-to-Digital Converter with Computation Module
34 OPA - Operational Amplifier
35 DAC - Digital-to-Analog Converter Module
36 CMP - Comparator Module
37 FVR - Fixed Voltage Reference
38 Temperature Indicator Module
39 ZCD - Zero-Cross Detection Module
40 Charge Pump
41 Instruction Set Summary
42 ICSP™ - In-Circuit Serial Programming™
43 Register Summary
44 Electrical Specifications
45 DC and AC Characteristics Graphs and Tables
46 Packaging Information
47 Appendix A: Revision History
Microchip Information

9.7.8 WREG

Working Data Register

Name:	WREG
Offset:	0x0009


Bit	7	6	5	4	3	2	1	0
	WREG[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – WREG[7:0]

On this page

Bits 7:0 – WREG[7:0]

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