19.1 Overview

Table 19-1. Port Availability per Device
DevicePORTAPORTBPORTC
14-pin devices●(1)●(3)
20-pin devices●(1)●(2)●
Note:
  1. Pins RA0 - RA5 only.
  2. Pins RB4 - RB7 only.
  3. Pins RC0 - RC5 only.

Each port has eight registers to control the operation. These registers are:

  • PORTx registers (reads the levels on the pins of the device)
  • LATx registers (output latch)
  • TRISx registers (data direction)
  • ANSELx registers (analog select)
  • WPUx registers (weak pull-up)
  • INLVLx (input level control)
  • SLRCONx registers (slew rate control)
  • ODCONx registers (open-drain control)

In this section, the generic names such as PORTx, LATx, TRISx, etc. can be associated with PORTA, PORTB, PORTC, etc., depending on availability per device.

A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in the following figure:

Figure 19-1. Generic I/O Port Operation