31.8.17 Period Value

Name: PER
Offset: 0x40
Reset: 0xFFFFFFFF
Property: Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 PER[17:10] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 15141312111098 
 PER[9:2] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 76543210 
 PER[1:0]DITHER[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 23:6 – PER[17:0] Period Value

These bits hold the value of the period buffer register.

Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTIONBits [23:m]
0x0 - NONE23:0
0x1 - DITH423:4
0x2 - DITH523:5
0x3 - DITH623:6 (depicted)

Bits 5:0 – DITHER[5:0] Dithering Cycle Number

These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTIONBits [n:0]
0x0 - NONE-
0x1 - DITH43:0
0x2 - DITH54:0
0x3 - DITH65:0 (depicted)