19.8.4 Read Request

Name: READREQ
Offset: 0x02
Reset: 0x0010
Property: -

Bit 15141312111098 
 RREQRCONT       
Access WR/W 
Reset 00 
Bit 76543210 
   ADDR[5:0] 
Access RRRRRR 
Reset 010000 

Bit 15 – RREQ Read Request

Writing a zero to this bit has no effect.

Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).

Bit 14 – RCONT Read Continuously

Writing a zero to this bit disables continuous synchronization.

Writing a one to this bit enables continuous synchronization of the register pointed to by READREQ.ADDR. The register value will be synchronized automatically every time the register is updated. READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ bit is required to be set once the RCONT bit is set.

This bit is cleared when an RTC register is written.

Note: Once the continuous synchronization is enabled, the first write in the COUNT/CLOCK register will be stalled for a maximum of 6 APB + 6 RTC clock cycles (the time for the on-going read synchronization to complete).

Bits 5:0 – ADDR[5:0] Address

These bits select the offset of the register that needs read synchronization. In the RTC only COUNT and CLOCK, which share the same address, are available for read synchronization. Therefore, ADDR is a read-only constant of 0x10.