24.8.2 Channel
| Name: | CHANNEL |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Write-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EDGSEL[1:0] | PATH[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EVGEN[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SWEVT | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHANNEL[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 27:26 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
| EDGSEL[1:0] | Name | Description |
|---|---|---|
| 0x0 | NO_EVT_OUTPUT | No event output when using the resynchronized or synchronous path |
| 0x1 | RISING_EDGE | Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path |
| 0x2 | FALLING_EDGE | Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path |
| 0x3 | BOTH_EDGES | Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path |
Bits 25:24 – PATH[1:0] Path Selection
These bits are used to choose the path to be used by the selected channel.
The path choice can be limited by the channel source.
| PATH[1:0] | Name | Description |
|---|---|---|
| 0x0 | SYNCHRONOUS | Synchronous path |
| 0x1 | RESYNCHRONIZED | Resynchronized path |
| 0x2 | ASYNCHRONOUS | Asynchronous path |
| 0x3 | Reserved |
Bits 22:16 – EVGEN[6:0] Event Generator Selection
These bits are used to choose which event generator to connect to the selected channel.
| Value | Event Generator | Description |
|---|---|---|
| 0x00 | NONE | No event generator selected |
| 0x01 | RTC CMP0 | Compare 0 (mode 0 and 1) or Alarm 0 (mode 2) |
| 0x02 | RTC CMP1 | Compare 1 |
| 0x03 | RTC OVF | Overflow |
| 0x04 | RTC PER0 | Period 0 |
| 0x05 | RTC PER1 | Period 1 |
| 0x06 | RTC PER2 | Period 2 |
| 0x07 | RTC PER3 | Period 3 |
| 0x08 | RTC PER4 | Period 4 |
| 0x09 | RTC PER5 | Period 5 |
| 0x0A | RTC PER6 | Period 6 |
| 0x0B | RTC PER7 | Period 7 |
| 0x0C |
EIC EXTINT0 |
External Interrupt 0 |
| 0x0D | EIC EXTINT1 | External Interrupt 1 |
| 0x0E | EIC EXTINT2 | External Interrupt 2 |
| 0x0F | EIC EXTINT3 | External Interrupt 3 |
| 0x10 | EIC EXTINT4 | External Interrupt 4 |
| 0x11 | EIC EXTINT5 | External Interrupt 5 |
| 0x12 | EIC EXTINT6 | External Interrupt 6 |
| 0x13 | EIC EXTINT7 | External Interrupt 7 |
| 0x14 | EIC EXTINT8 | External Interrupt 8 |
| 0x15 | EIC EXTINT9 | External Interrupt 9 |
| 0x16 | EIC EXTINT10 | External Interrupt 10 |
| 0x17 | EIC EXTINT11 | External Interrupt 11 |
| 0x18 | EIC EXTINT12 | External Interrupt 12 |
| 0x19 | EIC EXTINT13 | External Interrupt 13 |
| 0x1A | EIC EXTINT14 | External Interrupt 14 |
| 0x1B | EIC EXTINT15 | External Interrupt 15 |
| 0x1C | Reserved | |
| 0x1D | Reserved | |
| 0x1E | DMAC CH0 | Channel 0 |
| 0x1F | DMAC CH1 | Channel 1 |
| 0x20 | DMAC CH2 | Channel 2 |
| 0x21 | DMAC CH3 | Channel 3 |
| 0x22 | TCC0 OVF | Overflow |
| 0x23 | TCC0 TRG | Trig |
| 0x24 | TCC0 CNT | Counter |
| 0x25 | TCC0_MCX0 | Match/Capture 0 |
| 0x26 | TCC0_MCX1 | Match/Capture 1 |
| 0x27 | TCC0_MCX2 | Match/Capture 2 |
| 0x28 | TCC0_MCX3 | Match/Capture 3 |
| 0x29 | TCC1 OVF | Overflow |
| 0x2A | TCC1 TRG | Trig |
| 0x2B | TCC1 CNT | Counter |
| 0x2C | TCC1_MCX0 | Match/Capture 0 |
| 0x2D | TCC1_MCX1 | Match/Capture 1 |
| 0x2E | TCC2 OVF | Overflow |
| 0x2F | TCC2 TRG | Trig |
| 0x30 | TCC2 CNT | Counter |
| 0x31 | TCC2_MCX0 | Match/Capture 0 |
| 0x32 | TCC2_MCX1 | Match/Capture 1 |
| 0x33 | TC3 OVF | Overflow/Underflow |
| 0x34 | TC3 MC0 | Match/Capture 0 |
| 0x35 | TC3 MC1 | Match/Capture 1 |
| 0x36 | TC4 OVF | Overflow/Underflow |
| 0x37 | TC4 MC0 | Match/Capture 0 |
| 0x38 | TC4 MC1 | Match/Capture 1 |
| 0x39 | TC5 OVF | Overflow/Underflow |
| 0x3A | TC5 MC0 | Match/Capture 0 |
| 0x3B | TC5 MC1 | Match/Capture 1 |
| 0x3C |
TC6 OVF |
Overflow/Underflow |
| 0x3D |
TC6 MC0 |
Match/Capture 0 |
| 0x3E |
TC6 MC1 |
Match/Capture 1 |
| 0x3F |
TC7 OVF |
Overflow/Underflow |
| 0x40 |
TC7 MC0 |
Match/Capture 0 |
| 0x41 |
TC7 MC1 |
Match/Capture 1 |
| 0x42 | ADC RESRDY | Result Ready |
| 0x43 | ADC WINMON | Window Monitor |
| 0x44 | AC COMP0 | Comparator 0 |
| 0x45 | AC COMP1 | Comparator 1 |
| 0x46 | AC WIN0 | Window 0 |
| 0x47 |
DAC EMPTY |
Data Buffer Empty |
| 0x48 |
PTC EOC |
End of Conversion |
| 0x49 |
PTC WCOMP |
Window Comparator |
| 0x4A | AC COMP2 | Comparator 2 |
| 0x4B | AC COMP3 | Comparator 3 |
| 0x4C | AC WIN1 | Window 1 |
| 0x4D | TCC3 OVF | Overflow |
| 0x4E | TCC3 TRG | Trigger |
| 0x4F | TCC3 CNT | Counter |
| 0x50 | TCC3_MCX0 | Match/Capture 0 |
| 0x51 | TCC3_MCX1 | Match/Capture 1 |
| 0x52 | TCC3_MCX2 | Match/Capture 2 |
| 0x53 | TCC3_MCX3 | Match/Capture 3 |
| 0x54-0x7F | Reserved | Reserved |
Bit 8 – SWEVT Software Event
This bit is used to insert a software event on the channel selected by the CHANNEL.CHANNEL bit group.
This bit has the same behavior similar to an event.
This bit must be written together with CHANNEL.CHANNEL using a 16-bit write.
Writing a zero to this bit has no effect.
Writing a one to this bit will trigger a software event for the corresponding channel.
This bit will always return zero when read.
Bits 3:0 – CHANNEL[3:0] Channel Selection
These bits are used to select the channel to be set up or read from.