29.6.8.1 DMA Operation
Each Serializer can be connected either to
one single DMAC channel or to one DMAC channel per data slot in stereo mode. This is
selected by writing the SERCTRLm.DMA bit:
| SERCTRLm.DMA | Mode | Slot Parity | DMA Request Trigger |
|---|---|---|---|
| 0 | Receiver | all | I2S_DMAC_ID_RX_m |
| Transmitter | all | I2S_DMAC_ID_TX_m | |
| 1 | Receiver | even | I2S_DMAC_ID_RX_0 |
| odd | I2S_DMAC_ID_RX_1 | ||
| Transmitter | even | I2S_DMAC_ID_TX_0 | |
| odd | I2S_DMAC_ID_TX_1 |
The DMAC reads from the DATAm register and writes to the DATAm register for all data slots, successively.
The DMAC transfers may use 32-, 16- or or 8-bit transactions according to the value of the SERCTRLm.DATASIZE field. 8-bit compact stereo uses 16-bit and 16-bit compact stereo uses 32-bit transactions.