20.8.1 Control

Name: CTRL
Offset: 0x00
Reset: 0x00X0
Property: PAC Write-Protection, Enable-Protected

Bit 15141312111098 
     LVLENx3LVLENx2LVLENx1LVLENx0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
      CRCENABLEDMAENABLESWRST 
Access R/WR/WR/W 
Reset 000 

Bits 8, 9, 10, 11 – LVLENx Priority Level x Enable

When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all requests with the corresponding level will be ignored.

For details on arbitration schemes, refer to the Arbitration section.

These bits are not enable-protected.

ValueDescription
0 Transfer requests for Priority level x will not be handled.
1 Transfer requests for Priority level x will be handled.

Bit 2 – CRCENABLE CRC Enable

Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared (CRCSTATUS. CRCBUSY). The bit is zero when the CRC is disabled.

Writing a '1' to this bit will enable the CRC calculation.

ValueDescription
0 The CRC calculation is disabled.
1 The CRC calculation is enabled.

Bit 1 – DMAENABLE DMA Enable

Setting this bit will enable the DMA module.

Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed.

This bit is not enable-protected.

ValueDescription
0 The peripheral is disabled.
1 The peripheral is enabled.

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error.

ValueDescription
0 There is no Reset operation ongoing.
1 A Reset operation is ongoing.