20.8.19 Channel Control B
Name: | CHCTRLB |
Offset: | 0x44 |
Reset: | 0x00000000 |
Property: | PAC Write Protection, Enable-Protected |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
CMD[1:0] | |||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TRIGACT[1:0] | |||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
TRIGSRC[5:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
LVL[1:0] | EVOE | EVIE | EVACT[2:0] | ||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 25:24 – CMD[1:0] Software Command
These bits define the software commands. Refer to Channel Suspend and Channel Resume and Next Suspend Skip.
These bits are not enable-protected.
CMD[1:0] | Name | Description |
---|---|---|
0x0 | NOACT | No action |
0x1 | SUSPEND | Channel suspend operation |
0x2 | RESUME | Channel resume operation |
0x3 | - | Reserved |
Bits 23:22 – TRIGACT[1:0] Trigger Action
These bits define the trigger action used for a transfer.
TRIGACT[1:0] | Name | Description |
---|---|---|
0x0 | BLOCK | One trigger required for each block transfer |
0x1 | - | Reserved |
0x2 | BEAT | One trigger required for each beat transfer |
0x3 | TRANSACTION | One trigger required for each transaction |
Bits 13:8 – TRIGSRC[5:0] Trigger Source
These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.
Value | Name | Description |
---|---|---|
0x00 | DISABLE | Only software/event triggers |
0x01 | SERCOM0 RX | SERCOM0 RX Trigger |
0x02 | SERCOM0 TX | SERCOM0 TX Trigger |
0x03 | SERCOM1 RX | SERCOM1 RX Trigger |
0x04 | SERCOM1 TX | SERCOM1 TX Trigger |
0x05 | SERCOM2 RX | SERCOM2 RX Trigger |
0x06 | SERCOM2 TX | SERCOM2 TX Trigger |
0x07 | SERCOM3 RX | SERCOM3 RX Trigger |
0x08 | SERCOM3 TX | SERCOM3 TX Trigger |
0x09 | SERCOM4 RX | SERCOM4 RX Trigger |
0x0A | SERCOM4 TX | SERCOM4 TX Trigger |
0x0B | SERCOM5 RX | SERCOM5 RX Trigger |
0x0C | SERCOM5 TX | SERCOM5 TX Trigger |
0x0D | TCC0 OVF | TCC0 Overflow Trigger |
0x0E | TCC0 MC0 | TCC0 Match/Compare 0 Trigger |
0x0F | TCC0 MC1 | TCC0 Match/Compare 1 Trigger |
0x10 | TCC0 MC2 | TCC0 Match/Compare 2 Trigger |
0x11 | TCC0 MC3 | TCC0 Match/Compare 3 Trigger |
0x12 | TCC1 OVF | TCC1 Overflow Trigger |
0x13 | TCC1 MC0 | TCC1 Match/Compare 0 Trigger |
0x14 | TCC1 MC1 | TCC1 Match/Compare 1 Trigger |
0x15 | TCC2 OVF | TCC2 Overflow Trigger |
0x16 | TCC2 MC0 | TCC2 Match/Compare 0 Trigger |
0x17 | TCC2 MC1 | TCC2 Match/Compare 1 Trigger |
0x18 | TC3 OVF | TC3 Overflow Trigger |
0x19 | TC3 MC0 | TC3 Match/Compare 0 Trigger |
0x1A | TC3 MC1 | TC3 Match/Compare 1 Trigger |
0x1B | TC4 OVF | TC4 Overflow Trigger |
0x1C | TC4 MC0 | TC4 Match/Compare 0 Trigger |
0x1D | TC4 MC1 | TC4 Match/Compare 1 Trigger |
0x1E | TC5 OVF | TC5 Overflow Trigger |
0x1F | TC5 MC0 | TC5 Match/Compare 0 Trigger |
0x20 | TC5 MC1 | TC5 Match/Compare 1 Trigger |
0x21 | TC6 OVF | TC6 Overflow Trigger |
0x22 | TC6 MC0 | TC6 Match/Compare 0 Trigger |
0x23 | TC6 MC1 | TC6 Match/Compare 1 Trigger |
0x24 | TC7 OVF | TC7 Overflow Trigger |
0x25 | TC7 MC0 | TC7 Match/Compare 0 Trigger |
0x26 | TC7 MC1 | TC7 Match/Compare 1 Trigger |
0x27 | ADC RESRDY | ADC Result Ready Trigger |
0x28 | DAC EMPTY | DAC Empty Trigger |
0x29 | I2S RX 0 | I2S RX 0 Trigger |
0x2A | I2S RX 1 | I2S RX 1 Trigger |
0x2B | I2S TX 0 | I2S TX 0 Trigger |
0x2C | I2S TX 0 | I2S TX 1 Trigger |
0x2D | TCC3 OVF | TCC3 Overflow Trigger |
0x2E | TCC3 MC0 | TCC3 Match/Compare 0 Trigger |
0x2F | TCC3 MC1 | TCC3 Match/Compare 1 Trigger |
0x30 | TCC3 MC2 | TCC3 Match/Compare 2 Trigger |
0x31 | TCC3 MC3 | TCC3 Match/Compare 3 Trigger |
Bits 6:5 – LVL[1:0] Channel Arbitration Level
These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For further details on arbitration schemes, refer to Arbitration.
These bits are not enable-protected.
TRIGACT[1:0] | Name | Description |
---|---|---|
0x0 | LVL0 | Channel Priority Level 0 |
0x1 | LVL1 | Channel Priority Level 1 |
0x2 | LVL2 | Channel Priority Level 2 |
0x3 | LVL3 | Channel Priority Level 3 |
Bit 4 – EVOE Channel Event Output Enable
This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).
This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.
Value | Description |
---|---|
0 | Channel event generation is disabled |
1 | Channel event generation is enabled |
Bit 3 – EVIE Channel Event Input Enable
This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.
Value | Description |
---|---|
0 | Channel event action will not be executed on any incoming event |
1 | Channel event action will be executed on any incoming event |
Bits 2:0 – EVACT[2:0] Event Input Action
These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set.
These bits are available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.
EVACT[2:0] | Name | Description |
---|---|---|
0x0 | NOACT | No action |
0x1 | TRIG | Normal Transfer and Conditional Transfer on Strobe trigger |
0x2 | CTRIG | Conditional transfer trigger |
0x3 | CBLOCK | Conditional block transfer |
0x4 | SUSPEND | Channel suspend operation |
0x5 | RESUME | Channel resume operation |
0x6 | SSKIP | Skip next block suspend action |
0x7 | - | Reserved |