20.8.19 Channel Control B

This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHCTRLB
Offset: 0x44
Reset: 0x00000000
Property: PAC Write Protection, Enable-Protected

Bit 3130292827262524 
       CMD[1:0] 
Access R/WR/W 
Reset 00 
Bit 2322212019181716 
 TRIGACT[1:0]       
Access R/WR/W 
Reset 00 
Bit 15141312111098 
   TRIGSRC[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
  LVL[1:0]EVOEEVIEEVACT[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 25:24 – CMD[1:0] Software Command

These bits define the software commands. Refer to Channel Suspend and Channel Resume and Next Suspend Skip.

These bits are not enable-protected.

CMD[1:0]NameDescription
0x0NOACTNo action
0x1SUSPENDChannel suspend operation
0x2RESUMEChannel resume operation
0x3-Reserved

Bits 23:22 – TRIGACT[1:0] Trigger Action

These bits define the trigger action used for a transfer.

TRIGACT[1:0]NameDescription
0x0BLOCKOne trigger required for each block transfer
0x1-Reserved
0x2BEATOne trigger required for each beat transfer
0x3TRANSACTIONOne trigger required for each transaction

Bits 13:8 – TRIGSRC[5:0] Trigger Source

These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.

ValueNameDescription
0x00DISABLEOnly software/event triggers
0x01SERCOM0 RXSERCOM0 RX Trigger
0x02SERCOM0 TXSERCOM0 TX Trigger
0x03SERCOM1 RXSERCOM1 RX Trigger
0x04SERCOM1 TXSERCOM1 TX Trigger
0x05SERCOM2 RXSERCOM2 RX Trigger
0x06SERCOM2 TXSERCOM2 TX Trigger
0x07SERCOM3 RXSERCOM3 RX Trigger
0x08SERCOM3 TXSERCOM3 TX Trigger
0x09SERCOM4 RXSERCOM4 RX Trigger
0x0ASERCOM4 TXSERCOM4 TX Trigger
0x0BSERCOM5 RXSERCOM5 RX Trigger
0x0CSERCOM5 TXSERCOM5 TX Trigger
0x0DTCC0 OVFTCC0 Overflow Trigger
0x0ETCC0 MC0TCC0 Match/Compare 0 Trigger
0x0FTCC0 MC1TCC0 Match/Compare 1 Trigger
0x10TCC0 MC2TCC0 Match/Compare 2 Trigger
0x11TCC0 MC3TCC0 Match/Compare 3 Trigger
0x12TCC1 OVFTCC1 Overflow Trigger
0x13TCC1 MC0TCC1 Match/Compare 0 Trigger
0x14TCC1 MC1TCC1 Match/Compare 1 Trigger
0x15TCC2 OVFTCC2 Overflow Trigger
0x16TCC2 MC0TCC2 Match/Compare 0 Trigger
0x17TCC2 MC1TCC2 Match/Compare 1 Trigger
0x18TC3 OVFTC3 Overflow Trigger
0x19TC3 MC0TC3 Match/Compare 0 Trigger
0x1ATC3 MC1TC3 Match/Compare 1 Trigger
0x1BTC4 OVFTC4 Overflow Trigger
0x1CTC4 MC0TC4 Match/Compare 0 Trigger
0x1DTC4 MC1TC4 Match/Compare 1 Trigger
0x1ETC5 OVFTC5 Overflow Trigger
0x1FTC5 MC0TC5 Match/Compare 0 Trigger
0x20TC5 MC1TC5 Match/Compare 1 Trigger
0x21TC6 OVFTC6 Overflow Trigger
0x22TC6 MC0TC6 Match/Compare 0 Trigger
0x23TC6 MC1TC6 Match/Compare 1 Trigger
0x24TC7 OVFTC7 Overflow Trigger
0x25TC7 MC0TC7 Match/Compare 0 Trigger
0x26TC7 MC1TC7 Match/Compare 1 Trigger
0x27ADC RESRDYADC Result Ready Trigger
0x28DAC EMPTYDAC Empty Trigger
0x29I2S RX 0I2S RX 0 Trigger
0x2AI2S RX 1I2S RX 1 Trigger
0x2BI2S TX 0I2S TX 0 Trigger
0x2CI2S TX 0I2S TX 1 Trigger
0x2DTCC3 OVFTCC3 Overflow Trigger
0x2ETCC3 MC0TCC3 Match/Compare 0 Trigger
0x2FTCC3 MC1TCC3 Match/Compare 1 Trigger
0x30TCC3 MC2TCC3 Match/Compare 2 Trigger
0x31 TCC3 MC3TCC3 Match/Compare 3 Trigger

Bits 6:5 – LVL[1:0] Channel Arbitration Level

These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For further details on arbitration schemes, refer to Arbitration.

These bits are not enable-protected.

TRIGACT[1:0]NameDescription
0x0LVL0Channel Priority Level 0
0x1LVL1Channel Priority Level 1
0x2LVL2Channel Priority Level 2
0x3LVL3Channel Priority Level 3

Bit 4 – EVOE Channel Event Output Enable

This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).

This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

ValueDescription
0Channel event generation is disabled
1Channel event generation is enabled

Bit 3 – EVIE Channel Event Input Enable

This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

ValueDescription
0Channel event action will not be executed on any incoming event
1Channel event action will be executed on any incoming event

Bits 2:0 – EVACT[2:0] Event Input Action

These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set.

These bits are available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

EVACT[2:0]NameDescription
0x0NOACTNo action
0x1TRIGNormal Transfer and Conditional Transfer on Strobe trigger
0x2CTRIGConditional transfer trigger
0x3CBLOCKConditional block transfer
0x4SUSPENDChannel suspend operation
0x5RESUMEChannel resume operation
0x6SSKIPSkip next block suspend action
0x7-Reserved