18.8.2 Configuration

Name: CONFIG
Offset: 0x1
Reset: N/A - Loaded from NVM User Row at startup
Property: Write-Protected, Enable-Protected, Write-Synchronized

Bit 76543210 
 WINDOW[3:0]PER[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxxx 

Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period

In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles.

These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.

ValueDescription
0x0 8 clock cycles
0x1 16 clock cycles
0x2 32 clock cycles
0x3 64 clock cycles
0x4 128 clock cycles
0x5 256 clocks cycles
0x6 512 clocks cycles
0x7 1024 clock cycles
0x8 2048 clock cycles
0x9 4096 clock cycles
0xA 8192 clock cycles
0xB 16384 clock cycles
0xC-0xF Reserved

Bits 3:0 – PER[3:0] Time-Out Period

These bits determine the watchdog time-out period as a number of GCLK_WDT clock cycles. In window mode operation, these bits define the open window period.

These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.

ValueDescription
0x0 8 clock cycles
0x1 16 clock cycles
0x2 32 clock cycles
0x3 64 clock cycles
0x4 128 clock cycles
0x5 256 clocks cycles
0x6 512 clocks cycles
0x7 1024 clock cycles
0x8 2048 clock cycles
0x9 4096 clock cycles
0xA 8192 clock cycles
0xB 16384 clock cycles
0xC-0xF Reserved