43.4.7 Analog-to-Digital Converter (ADC) Conversion Timing Specifications

Table 43-13.
Standard Operating Conditions (unless otherwise stated)
Param No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
AD20	T_AD	ADC Clock Period	0.5	—	9	μs	Using F_OSC as the ADC clock source
AD20A	T_AD	ADC Clock Period	—	2	—	μs	Using ADCRC as the ADC clock source
AD21*	T_CNV	Conversion Time	—	14T_AD+2T_CY	—	T_AD	Using F_OSC as the ADC clock source
AD21A*	T_CNV	Conversion Time	—	16T_AD+2T_CY	—	T_AD	Using ADCRC as the ADC clock source
AD22*	T_HCD	Sample-and-Hold Capacitor Disconnect Time	—	2T_AD+1T_CY	—	T_AD	Using F_OSC as the ADC clock source
AD22A*	T_HCD	Sample-and-Hold Capacitor Disconnect Time	—	3T_AD+2T_CY	—	T_AD	Using ADCRC as the ADC clock source
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. * These parameters are characterized but not tested.

Figure 43-9. ADC Conversion Timing (ADC Clock F_OSC-Based)

Figure 43-10. ADC Conversion Timing (ADC Clock from ADCRC)

Note:

If the ADC clock source is selected as ADCRC, a time of T_CY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.