3.2.3 DDR Controller and DDR3L Memory Device

The SDRAM memory interface is made of the Universal DDR Memory Controller (UDDRC) and the physical layer interface (DDR3PHY). The UDDRC receives transactions from the internal buses. These transactions are queued internally and scheduled for access in order to the DDR-SDRAM while satisfying the DDR-SDRAM protocol timing requirements, transaction priorities, and dependencies between transactions.

One external DDR3L memory (8-Gbit Alliance Memory, Inc. AS4C512M16D3LA-10BIN) is used as system RAM, totaling 1 GByte of SDRAM on the board. The memory bus is 16 bits wide and operates with a frequency of up to 533 MHz.

Figure 3-13. Processor MPDDRC Controller

The DDR_VREF pin serves as a voltage reference input for the DDR I/Os when DDR or LPDDR external SDRAM memories are used. The DDR_VREF level is obtained from VDDIODDR using a ½ resistor voltage divider.

Figure 3-14. DDR_VREF Source

Figure 3-15. DDR3L SDRAM Device