3.2 Main Configuration and Control

XIN

Input

Main clock oscillator input

XOUT

Output

Main clock oscillator output

XIN32

Input

Slow clock oscillator input

XOUT32

Output

Slow clock oscillator output

SHDN

Output

Signal used to enable and disable an external power supply circuit

WKUP0

Input

Event detection input pin used to wake up the processor from Shutdown state

JTAGSEL

Input

When pulled high, enables the JTAG boundary scan

NRST

Input

Processor reset input

NRST_OUT

Output

Peripheral reset output

TST

Input

Reserved for processor manufacturing tests

LPM

Output

Low-Power mode enable output

QSPI0_CAL

Input

QSPI0 cell calibration

SDMMC0_CAL

Input

SDMMC0 cell calibration

SDMMC1_CAL

Input

SDMMC1 cell calibration

SDMMC2_CAL

Input

SDMMC2 cell calibration

AUDIOCLK

Output

Audio PLL clock output

HHSA_DM

Bidirectional

USB A negative differential signal

HHSA_DP

Bidirectional

USB A positive differential signal

HHSRTUNE

Input

USB cell calibration

HHSB_DM

Bidirectional

USB B negative differential signal

HHSB_DP

Bidirectional

USB B positive differential signal

HHSC_DM

Bidirectional

USB C negative differential signal

HHSC_DP

Bidirectional

USB C positive differential signal

MIPI_CLK_N

Output

MIPI clock negative differential signal

MIPI_CLK_P

Output

MIPI clock positive differential signal

MIPI_DO_N

Output

MIPI data 0 negative differential signal

MIPI_DO_P

Output

MIPI data 0 positive differential signal

MIPI_D1_N

Output

MIPI data 1 negative differential signal

MIPI_D1_P

Output

MIPI data 1 positive differential signal

MIPI_D2_N

Output

MIPI data 2 negative differential signal

MIPI_D2_P

Output

MIPI data 2 positive differential signal

MIPI_D3_N

Output

MIPI data 3 negative differential signal

MIPI_D3_P

Output

MIPI data 3 positive differential signal

MIPI_REXT

Input

MIPI calibration cell

DIODE_N

Output

Reserved

DIODE_P

Output

Reserved

TEMP_GND

Input

GND